Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 881

16. Write 0x2000_2020 to DPRAM+0x500 to set up the RBASE and TBASE fields of the endpoint 0
parameter RAM.
17. Write 0x1818_0100 to DPRAM+0x504 to set up the RFCR, TFCR, and MRBLR fields of the
endpoint 0 parameter RAM.
18. Write 0x2000_2020 to DPRAM+0x508 to set up the RBPTR and TBPTR fields of the endpoint 0
parameter RAM.
19. Clear the TSTATE field of the endpoint 0 parameter RAM.
20. Write 0x2008_2028 to DPRAM+0x520 to set up the RBASE and TBASE fields of the endpoint 1
parameter RAM.
21. Write 0x1818_0100 to DPRAM+0x524 to set up the RFCR, TFCR, and MRBLR fields of the
endpoint 1 parameter RAM.
22. Write 0x2008_2028 to DPRAM+0x528 to set up the RBPTR and TBPTR fields of the endpoint 1
parameter RAM.
23. Clear the TSTATE field of the endpoint 1 parameter RAM.
24. Write 0x0020 to USEP0 for the host, control transfer, multi-packet.
25. Write 0x1100 to USEP1 for endpoint 1, interrupt transfer, one packet only.
26. Write 0x06 to USMOD for full-speed 12 Mbps signaling, local loopback configuration (test and
host modes set), and disable the USB.
27. Write 0x05 to the USAD for slave address 5.
28. Set USMOD[EN] to enable the USB controller.
29. Write 0x81 to the USCOM to start filling the Tx FIFO with endpoint 1 data ready for transmission
when an IN token is received.
30. Write 0x80 to the USCOM to start filling the Tx FIFO with endpoint 0 data ready for transmission.
The expected results are as follows:
• TxBD[Status and Control] of endpoint 0 should contain 0x3800.
• TxBD[Data Length] of endpoint 0 should contain 0x0003.
• TxBD[Status and Control] of endpoint 1 should contain 0x3C80.
• TxBD[Data Length] of endpoint 1 should contain 0x0003.
• RxBD[Status and Control] of endpoint 0 should contain 0x3C00.
• RxBD[Data Length] of endpoint 0 should contain 0x0005.
• The receive buffer of endpoint 0 should contain 0xABCD_122B, 0x42xx_xxxx.
Freescale Semiconductor
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Universal Serial Bus (USB)
31-33