Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 891

Bits Name
1–6 — Reserved and should be cleared.
7 M/S Master/slave. Configures the I
2
0 I C is a slave.
2
1 I C is a master.
2
32.5 I C Parameter RAM
2
The I C controller parameter RAM area, shown in
similar to the SCC general-purpose parameter RAM. Certain parameter RAM values, such as the
maximum receive buffer length (MRBLR), must be initialized by the user before the I
other parameters, used by the CPM, do not need initialization. Software usually does not access parameter
RAM entries once they are initialized; they should be changed only when the I
1
Offset Name
0x00 RBASE
0x02 TBASE
0x04 RFCR
0x05 TFCR
0x06 MRBLR
0x08 RSTATE
0x0C RPTR
0x10 RBPTR
0x12 RCOUNT Hword Rx internal byte count
Freescale Semiconductor
Table 32-5. I2COM Field Descriptions (continued)
2
C controller to operate as a master or a slave.
2
Table 32-6. I C Parameter RAM Memory Map
Width
Hword Rx/TxBD table base address. Indicate where the BD tables begin in the dual-port
RAM. Setting Rx/TxBD[W] in the last BD in each BD table determines how many BDs
Hword
are allocated for the Tx and Rx sections of the I
2
enabling the I C. Furthermore, do not configure BD tables of the I
other active controller's parameter RAM.
RBASE and TBASE should be divisible by eight.
Byte Rx/Tx function code. The value to appear on AT[1–3] when the associated SDMA
channel accesses memory. Also controls the byte-ordering convention for transfers.
Byte
See Figure 32-11 and
Hword Maximum receive buffer length. Defines the maximum number of bytes the I
receiver writes to a receive buffer before moving to the next buffer. The receiver writes
fewer bytes to the buffer than the MRBLR value if an error or end-of-frame occurs.
Receive buffers should not be smaller than MRBLR.
Transmit buffers are unaffected by MRBLR and can vary in length; the number of
bytes to be sent is specified in TxBD[Data Length].
MRBLR is not intended to be changed while the I
changed in a single bus cycle with one 16-bit move (not two 8-bit bus cycles
back-to-back). The change takes effect when the CP moves control to the next
RxBD. To guarantee the exact RxBD on which the change occurs, change MRBLR
2
only while the I C receiver is disabled. MRBLR should be greater than zero.
Word Rx internal state. Reserved for CPM use.
Word Rx internal data pointer
in the buffer to be accessed.
Hword RxBD pointer. Points to the next descriptor the receiver transfers data to when it is in
an idle state or to the current descriptor during frame processing for each I
channel. After a reset or when the end of the descriptor table is reached, the CP
initializes RBPTR to the value in RBASE. Most applications should not write RBPTR,
but it can be modified when the receiver is disabled or when no receive buffer is used.
and decremented with every byte the SDMA channels write.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Table 32-6, is used for the general I
Description
2
C. Initialize RBASE/TBASE before
Table 32-7.
2
C is operating. However it can be
2
is updated by the SDMA channels to show the next address
2
is a down-count value that is initialized with the MRBLR value
2
I C Controller
2
C parameters. It is
2
C is enabled, while
2
C is inactive.
2
C to overlap any
2
C
2
C
32-9