Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 258

Memory Management Unit
Table 8-8 describes MD_CTR fields.
Bits Name
0 GPM
1 PPM
2 CIDEF
3 WTDEF
4 RSV4D
5 TWAM
6 PPCS
7–18 —
19–23 DTLB_INDX DTLB index. Points to DTLB entry to be loaded. Decremented every DTLB update.
24–31 —
IMMU/DMMU Effective Page Number Register (M x _EPN)
8.8.3
The effective page number registers (MI_EPN and MD_EPN), shown in
loaded into a TLB entry
0
Field
Reset
R/W
16
Field EPN
Reset —
R/W R/W
SPR
Figure 8-8. IMMU/DMMU Effective Page Number Register (M x _EPN)
8-16
Table 8-8. MD_CTR Field Descriptions
Group protection mode
0 Default mode
1 Domain manager mode
Page protection mode
0 Page resolution of protection
1 1-Kbyte resolution of protection for 4-Kbyte pages
CI default when the DMMU is disabled (MSR[DR] = 0)
0 Caching is allowed.
1 Caching is inhibited.
WT default when the DMMU is disabled (MSR[DR] = 0)
Reserve four DTLB entries. See
0 DTLB_INDX decremented modulo 32
1 DTLB_INDX decremented modulo 28
Tablewalk assist mode
0 1-Kbyte subpage hardware assist
1 4-Kbyte page hardware assist (default)
Privilege/user state compare mode
0 Ignore user/supervisor state during address compare
1 Account for user/supervisor state according to MD_RPN[24–27]
Reserved. Ignored on write, returns 0 on read
Reserved. Ignored on write, returns 0 on read
0000_0000_0000_0000
19 20 21 22
— EV
0 0
R R/W
787 (MI_EPN); 795 (MD_EPN)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Section 8.10.2, "Locking TLB Entries."
Figure
EPN
R/W
23
—
0
R
8-8, contain the EA to be
15
27 28 31
ASID
0
R/W
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