Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 386

External Bus Interface
Figure 13-9 shows the basic time of a single-beat write cycle with one wait state.
CLKOUT
BR
BG
BB
A[0:31]
R/W
TSIZ[0:1], AT[0:3]
BURST
TS
Data
TA
Figure 13-9. Basic Timing: Single-Beat Write Cycle, One Wait State
The general case of single-beat transfers assumes that external memory has a 32-bit port size. As
demonstrated in Figure 13-10, the MPC885 provides an effective mechanism for interfacing with 16- and
8-bit port size memories by allowing transfers to these devices when they are controlled by the internal
memory controller.
13-12
Receive BG and BB negated
Assert BB, drive address and assert TS
Wait State
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Data is Sampled
Freescale Semiconductor