Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 793

13. Initialize the RxBD. Assume the Rx buffer is at 0x0000_1000 in main memory. Write 0xB000 to
RxBD[Status and Control], 0x0000 to RxBD[Data Length] (optional), and 0x0000_1000 to
RxBD[Buffer Pointer].
14. Initialize the TxBD. Assume the Tx buffer is at 0x0000_2000 in main memory and contains five
8-bit characters. Write 0xBC00 to TxBD[Status and Control], 0x0005 to TxBD[Data Length], and
0x0000_2000 to TxBD[Buffer Pointer].
15. Write 0xFFFF to SCCE to clear any previous events.
16. Write 0x0013 to SCCM to enable the TXE, TXB, and RXB interrupts.
17. Write 0x2000_0000 to the CPM interrupt mask register (CIMR) to allow SCC2 to generate a
system interrupt. The CICR should also be initialized.
18. Write 0x0000_1980 to GSMR_H2 to configure the transparent channel.
19. Write 0x0000_0000 to GSMR_L2 to configure CTS and CD to automatically control transmission
and reception (DIAG bits). Normal operation of the transmit clock is used. Note that the transmitter
(ENT) and receiver (ENR) are not enabled yet.
20. Write 0x0000_0030 to GSMR_L2 to enable the SCC2 transmitter and receiver. This additional
write ensures that the ENT and ENR bits are enabled last.
Note that after 5 bytes are sent, the Tx buffer is closed and after 16 bytes are received the Rx buffer is
closed. Any data received after 16 bytes causes a busy (out-of-buffers) condition since only one RxBD is
prepared.
Freescale Semiconductor
MPC885 PowerQUICC Family Reference Manual, Rev. 2
SCC Transparent Mode
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