Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 314

System Interface Unit
and the count resumes with a new value in the PITC. If the PTE bit is not set, the PIT is unable to count
and retains the old count value. Reading the PIT does not affect it.
PITCLK
Clock
The time-out period is calculated as follows:
10.10.1 Periodic Interrupt Status and Control Register (PISCR)
The periodic interrupt status and control register (PISCR), shown in
request level and status bits. It also controls the 16 bits to be loaded in a modulus counter. Note that PISCR
is a keyed register. It must be unlocked in PISCRK before it can be written.
0
Field
Reset
R/W
Addr
Figure 10-24. Periodic Interrupt Status and Control Register (PISCR)
This register is affected by HRESET but is not affected by SRESET.
Bits Name
0–7 PIRQ Periodic interrupt request level. Configures internal interrupt levels for periodic interrupts.
Figure 10-7
8 PS Periodic interrupt status. Can be cleared by writing a 1 to it (zero has no effect).
0 The PIT is unaffected.
1 The PIT has issued an interrupt.
9–12 — Reserved, should be cleared.
10-26
PTE PITC
Clock 16-Bit
Disable Modulus Counter
FRZ
Figure 10-23. Periodic Interrupt Timer Block Diagram
PITC 1 +
PIT = ------------------------ -
period
F
pitclk
PIRQ
0000_0000_0000_0000
(IMMR & 0xFFFF0000) + 0x240
Table 10-20. PISCR Field Descriptions
shows interrupt request levels.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
PS
PIE
PITC 1 +
= ----------------------------------------------------------- -
ExternalClock
⎛ ⎞
----------------------------------------- - ÷ 4
⎝ ⎠
1 o or o 128
Figure 10-24, contains the interrupt
7 8 9
PS —
R/W
Table 10-20
Description
PIT
Interrupt
12 13 14 15
PIE PITF PTE
describes PISCR fields.
Freescale Semiconductor