Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 283

Instructions
Order memory access: eieio
Cache control: icbi
1
Although a store (as well as mtspr for SPRs external to the core) issued to the LSU buffer frees the core pipeline, the
next load or store is not performed on the bus until it is free.
2
See Table 4-5.
3
Refer to Chapter 4, "MPC8xx Core Register Set."
4
See Section 4.1.1.1.1, "Condition Register (CR),"
5
DivisionLatency =
6
Division blockage = division latency.
7
Blockage of the multiply instruction is dependent on the next instruction.If the next instruction is a divide, the blockage
is 2 clocks; otherwise, the blockage is 1 clock.
8
Assumes nonspeculative aligned access, on-chip memory, and available bus. See
Load Instructions," Section 3.6.3.5, "Unaligned Accesses,"
9.2.1 Load/Store Instruction Timing
Table 9-2. summarizes load/store instruction timings. This table assumes zero wait-state memory
references on a parked bus and pipelined external memory accesses.
Instruction Type
Integer single target register load (aligned)
Integer single target register store (aligned)
Load/store multiple
1
N denotes the number of registers transferred.
Freescale Semiconductor
Table 9-1. Instruction Execution Timing (continued)
and
34 divisorLength
⎛
–
⇒
N oO ve r flow 3 + ------------------------------------------------------
⎝
4
------------------------------------------------------------------------------------------------------------------------
⇒
Ov er flo w 2
Table 9-2. Load/Store Instruction Timing
Data Cache External Memory Data Cache External Memory
2 cycles
1 cycle
1 + N
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Latency Blockage
1
1
Section 4.1.2.3.1, "Machine State Register (MSR)."
⎞
⎠
Where Overflow
Section 3.6.3.4, "Nonspeculative
and Section 9.2.1, "Load/Store Instruction Timing."
Latency
5 cycles
1 cycle
1
N 1 +
⎛ ⎞
3 N + +
--------------
⎝ ⎠
3
Instruction Execution Timing
Unit Serializing
LSU Next load/store
is synchronized
with ones before
LSU, No
I-cache
x
⎛ ⎞ or ⎛ ⎞
MaxNegativ eNumber
=
-- - ⎝ ⎠ --------------------------------------------------
⎝ ⎠
0 1 –
Cleared from LSU
2 cycles 5 cycles
2 cycles 5 cycles
1 + N
N 1 +
⎛ ⎞
3 N + +
--------------
⎝ ⎠
3
9-7