Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 259

Table 8-9 describes Mx_EPN fields.
Bits Name
0–19 EPN Effective page number for TLB entry. Default value is the EA of the last ITLB/DTLB miss
20–21 — Reserved. Ignored on write, undefined on read
22 EV TLB entry valid bit.
0 TLB entry is invalid
1 TLB entry is valid. EV is set to 1 on each ITLB/DTLB miss.
23–27 — Reserved. Ignored on write, returns 0 on read
28–31 ASID Address space ID of the ITLB/DTLB entry to be compared with M_CASID[CASID]. Loaded with
M_CASID on a TLB miss.
8.8.4 IMMU Tablewalk Control Register (MI_TWC)
The IMMU tablewalk control register (MI_TWC), shown in
group and page size of the entry to be loaded into the TLB.
0
Field
Reset
R/W
16
Field
Reset
R/W
SPR
Table 8-10 describes MI_TWC fields.
Bits Name
0–22 — Reserved. Ignored on write, returns 0 on read.
23–26 APG Access protection group. Up to 16 protection groups supported. Default for ITLB miss is 0
27 G Guarded memory attribute for entry
0 Nonguarded memory (default for ITLB miss)
1 Guarded memory
Freescale Semiconductor
Table 8-9. M x _EPN Field Descriptions
0000_0000_0000_0000
22
—
0
R/W
Figure 8-9. IMMU Tablewalk Control Register (MI_TWC)
Table 8-10. MI_TWC Field Descriptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Figure 8-9, contains the access protection
—
R/W
23 26 27
APG G
— —
R/W R/W
789
Description
Memory Management Unit
15
28 29 30 31
PS — V
— 0 —
R/W R/W R/W
8-17