Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 966

Powerquicc family

Table of Contents

ATM Overview

– Report on errors (CRC, length mismatch, message abort)

– Real-time timestamp capability to support connection timeout

— Segmentation:

– Segments CPCS_PDU directly from host memory

– Performs CPCS_PDU padding

– CRC32 generation

– Automatic last cell marking (in the PTI field of the cell header)

– Automatic CS_UU, CPI, and LENGTH insertion (in the last cell of the frame)

Supports AAL0 connections:

– Complete cell is stored in memory (with exception of the HEC).

– CRC10 pass/fail indication

– Optional interrupt per cell

– Reads a complete cell (with exception of the HEC) from the buffer

– Optional CRC10 insertion

Supports ATM port-to-port (PTP) cell switching:

— ALL0 cell PTP switching from the receive side to the transmit side without host software

intervention

— May be activated per channel as programmed in the RCT

— PTP connection between any combination of serial/UTOPIA/multi-PHY ports

— Cell scheduling may be done by one of the following methods:

– Using the ATM pace controller (APC) to reshape traffic

– Using the priority-based APC levels to maintain traffic shaping requirements over multiple

— BD table wrap counter (used for approximating total cell count)

— Error indication to host application (receiver busy, transmit queue full interrupts)

— Optional address translation

— Optional partial packet discard (PPD)

Physical layer (PHY) support:

— UTOPIA port provides glueless interface to PHY

– UTOPIA level 2 master (ATM side) or slave (PHY side) with cell-level handshake

– Supports UTOPIA external clock in both UTOPIA master and slave modes

– Supports UTOPIA level 2 multi-PHY interface for up to 31 PHYs

– Supports 8-bit UTOPIA data bus (using eight shared data signals in muxed mode or using

two separate 8-bit receive and transmit buses in split mode)

MPC885 PowerQUICC Family Reference Manual, Rev. 2

Freescale Semiconductor