Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 360

External Signals
Table 12-2. MPC875/MPC870 Signal Descriptions (continued)
Hard
Name
Reset
GPL_A0 High
GPL_B0
OE High
GPL_A1
GPL_B1
GPL_A[2:3] High
GPL_B[2:3]
CS[2:3]
UPWAITA Hi-Z
GPL_A4
UPWAITB Hi-Z
GPL_B4
GPL_A5 High
PORESET Hi-Z
RSTCONF Hi-Z
12-30
Number Type
C17 Output General-Purpose Line 0 on UPMA—This output reflects the value
specified in UPMA when an external transfer to a slave is
controlled by UPMA.
General-Purpose Line 0 on UPMB—This output reflects the value
specified in UPMB when an external transfer to a slave is
controlled by UPMB.
F13 Output Output Enable—Output asserted when the MPC875 initiates a
read access to an external slave controlled by the GPCM.
General-Purpose Line 1on UPMA—This output reflects the value
specified in UPMA when an external transfer to a slave is
controlled by UPMA.
General-Purpose Line 1 on UPMB—This output reflects the value
specified in UPMB when an external transfer to a slave is
controlled by UPMB.
E14, C16 Output General-Purpose Line 2 and 3 on UPMA—These outputs reflect
the value specified in UPMA when an external transfer to a slave
is controlled by UPMA.
General-Purpose Line 2 and 3 on UPMB—These outputs reflect
the value specified in UPMB when an external transfer to a slave
is controlled by UPMB.
Chip Select 2 and 3—These outputs enable peripheral or memory
devices at programmed addresses if they are appropriately
defined. The double drive capability for CS2 and CS3 is
independently defined for each signal in the SIU module
configuration register (SIUMCR).
D11 Bidirectional User Programmable Machine Wait A—This input is sampled as
defined by the user when an access to an external slave is
controlled by UPMA.
General-Purpose Line 4 on UPMA—This output reflects the value
specified in UPMA when an external transfer to a slave is
controlled by UPMA.
E12 Bidirectional User Programmable Machine Wait B—This input is sampled as
defined by the user when an access to an external slave is
controlled by UPMB.
General-Purpose Line 4 on UPMB—This output reflects the value
specified in UPMB when an external transfer to a slave is
controlled by UPMB.
D12 Output General-Purpose Line 5 on UPMA—This output reflects the value
specified in UPMA when an external transfer to a slave is
controlled by UPMA. This signal can also be controlled by UPMB.
D5 Input Power-on Reset—When asserted, this input causes the MPC875
to enter the power-on reset state.
C3 Input Reset Configuration—The MPC875 samples this input while
HRESET is asserted. If RSTCONF is asserted, the configuration
mode is sampled in the form of the hard reset configuration word
driven on the data bus. When RSTCONF is negated, the MPC875
uses the default configuration mode. Note that the initial base
address of internal registers is determined in this sequence.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Freescale Semiconductor