Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 323

The configuration of the MPC885 following the assertion of PORESET is shown in
Figure 11-7. While the PORESET input signal is being asserted, the core assumes the default reset
configuration (0x0000_0000). When PORESET is negated or the CLKOUT signal begins oscillation, the
hardware configuration is sampled from the data bus every nine clock cycles on the rising edge of
CLKOUT. The setup time required for the data bus is 15 cycles, and the maximum rise time of HRESET
should be less than six clock cycles. Refer to
Figure 11-5 shows a reset operation with a short PORESET signal assertion. Note that the configuration
of the MPC885 is determined from the signal levels driven on the D[0–31] signals following the assertion
of RSTCONF and the negation of HRESET.
CLKOUT
PORESET
INTPORESET
HRESET
RSTCONF
D[0:31]
Figure 11-5. Reset Configuration Sampling for Short PORESET Assertion
Figure 11-6 shows a reset operation with a long PORESET signal assertion.
CLKOUT
PORESET
INTPORESET
HRESET
RSTCONF
D[0:31]
Figure 11-6. Reset Configuration Sampling for Long PORESET Assertion
Freescale Semiconductor
Section 11.3.2, "Soft Reset,"
Default
Default
MPC885 PowerQUICC Family Reference Manual, Rev. 2
for more information.
TSUP
RSTCONF Controlled
TSUP
RSTCONF Controlled
Reset
Figure 11-5 through
11-7