Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 79

Table
Number
45-34 User Initialization (After Setting ECNTRL[ETHER_EN])................................................ 45-34
45-35 Receive Buffer Descriptor (RxBD) Field Description....................................................... 45-35
45-36 Transmit Buffer Descriptor (TxBD) Field Descriptions ..................................................... 45-38
46-1 Example Data Packet Descriptor .......................................................................................... 46-3
46-2 Estimated Bulk Data Encryption Performance (Mbps) ........................................................ 46-6
47-1 Module Base Address Map ................................................................................................... 47-1
47-2 Security Engine Memory Map Showing Register Details IMMR[14:15]=10)..................... 47-1
48-1 DEU Mode Register Field Descriptions ............................................................................... 48-3
48-2 DEU Key Size Register Field Descriptions .......................................................................... 48-4
48-3 DEU Reset Control Register Field Descriptions................................................................... 48-6
48-4 DEU Status Register ............................................................................................................. 48-7
48-5 DEU Interrupt Status Register Field Descriptions ................................................................ 48-8
48-6 DEU Interrupt Control Register Field Descriptions ........................................................... 48-10
48-7 MDEU Mode Register ........................................................................................................ 48-14
48-8 MDEU Reset Control Register Field Descriptions ............................................................. 48-17
48-9 MDEU Status Register Field Descriptions ......................................................................... 48-18
48-10 MDEU Interrupt Status Register Field Descriptions .......................................................... 48-19
48-11 MDEU Interrupt Control Register Field Descriptions ........................................................ 48-21
48-12 AESU Mode Register Field Descriptions ........................................................................... 48-25
48-13 AESU Reset Control Register Field Descriptions .............................................................. 48-28
48-14 AESU Status Register Field Descriptions........................................................................... 48-30
48-15 AESU Interrupt Status Register Field Descriptions............................................................ 48-31
48-16 AESU Interrupt Control Register Field Descriptions ......................................................... 48-33
48-17 Counter Modulus................................................................................................................. 48-36
49-1 Header Bit Definitions .......................................................................................................... 49-2
49-2 EU_SELECT Values ............................................................................................................. 49-3
49-3 Descriptor Types ................................................................................................................... 49-4
49-4 Descriptor Length Field Mapping......................................................................................... 49-5
49-5 Descriptor Pointer Field Mapping......................................................................................... 49-5
49-6 Descriptor Length/Pointer Mapping ..................................................................................... 49-6
49-7 Descriptor Pointer Field Mapping......................................................................................... 49-6
49-8 Descriptor_HMAC_Snoop_Non_AFEU .............................................................................. 49-8
50-1 Crypto-Channel Configuration Register Fields .................................................................... 50-2
50-2 Burst Size Definition............................................................................................................. 50-4
50-3 Crypto-Channel Pointer Status Register 1 Fields.................................................................. 50-5
50-4 Crypto-Channel Pointer Status Register 2 Fields.................................................................. 50-5
50-5 STATE Field Values .............................................................................................................. 50-7
50-6 Crypto-Channel Pointer Status Register Error Field Definitions.......................................... 50-9
50-7 Crypto-Channel Pointer Status Register PAIR_PTR Field Values........................................ 50-9
50-8 Crypto-Channel Current Descriptor Pointer Register Fields .............................................. 50-10
50-9 Fetch Register Fields........................................................................................................... 50-11
Freescale Semiconductor
Tables
Title
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Page
Number
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