Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 846

Serial Peripheral Interface (SPI)
3. Write RBASE and TBASE in the SPI parameter RAM to point to the RxBD and TxBD tables in
the dual-port RAM. Assuming one RxBD followed by one TxBD at the beginning of the dual-port
RAM, write RBASE with 0x0000 and TBASE with 0x0008.
4. Execute the
INIT RX AND TX PARAMETERS
5. Write 0x0001 to the SDCR to initialize the SDMA configuration register (SDCR).
6. Write RFCR and TFCR with 0x10 for normal operation.
7. Write MRBLR with the maximum number of bytes per Rx buffer. For this case, assume 16 bytes,
so MRBLR = 0x0010.
8. Initialize the RxBD. Assume the Rx buffer is at 0x0000_1000 in main memory. Write 0xB000 to
RxBD[Status and Control], 0x0000 to RxBD[Data Length] (optional), and 0x0000_1000 to
RxBD[Buffer Pointer].
9. Initialize the TxBD. Assume the Tx buffer is at 0x0000_2000 in main memory and contains five
8-bit characters. Write 0xB800 to TxBD[Status and Control], 0x0005 to TxBD[Data Length], and
0x0000_2000 to TxBD[Buffer Pointer].
10. Write 0xFF to SPIE to clear any previous events.
11. Write 0x37 to SPIM to enable all possible SPI interrupts.
12. Write 0x0000_0020 to the CPM interrupt mask register (CIMR). This sets CIMR[SPI] to enable
SPI-generated system interrupts. The CICR should also be initialized.
13. Write 0x0370 to SPMODE to enable normal operation (not loopback), master mode, SPI enabled,
8-bit characters, and the fastest speed possible.
14. Clear PBDAT[156], assuming PB156 is chosen above, to constantly assert the SPI select output
signal.
15. Set SPCOM[STR] to start the transfer.
After 5 bytes are sent, the TxBD is closed because TxBD[L] is set. The RxBD is closed when the TxBD
closes.
30.9 SPI Slave Programming Example
The following is an example initialization sequence to follow when the SPI is in slave mode. It is very
similar to the SPI master example, except that SPISEL is used instead of a general-purpose I/O signal (as
shown in Figure 30-2).
1. Set PBPAR[28–31] and PBDIR[28–31] to enable SPIMISO, SPIMOSI, SPICLK, and SPISEL,
then clear PBODR[28–31].
2. Assuming one RxBD at the beginning of the dual-port RAM followed by one TxBD, write RBASE
with 0x0000 and TBASE with 0x0008 in the SPI parameter RAM.
3. Write RFCR and TFCR with 0x10 for normal operation.
4. Execute the
INIT RX AND TX PARAMETERS
5. Write 0x0001 to SDCR.
6. Set MRBLR = 0x0010 for 16 bytes, the maximum number of bytes per buffer.
30-16
command by writing 0x0051 to CPCR.
command by writing 0x0051 to CPCR.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor