Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 884

Powerquicc family

Table of Contents

C Controller

The following is a list of the I

Two-signal interface (SDA on PB[27] and SCL on PB[26])

Support for master and slave I

Multiple-master environment support

Continuous transfer mode for autoscanning of a peripheral

Supports a maximum clock rate of 520 KHz (with a CPM utilization of 25%), assuming a 25-MHz

system clock.

Independent, programmable baud-rate generator

Supports 7-bit I

C addressing

Open-drain output signals allow multiple master configuration

Local loopback capability for testing

C Controller Clocking and Signal Functions

C controller can be configured as a master or slave for the serial channel. As a master, the controller's

BRG provides the transfer clock. The I

described in

Section 14.3, "Clock Signals."

SDA and SCL are bidirectional signals connected to a positive supply voltage through an external pull-up

resistor. When the bus is free, both signals are pulled high. The general I

C controller is the master, the SCL clock output, taken directly from the I

data in and transmit data out through SDA. The transmitter arbitrates for the bus during transmission and

aborts if it loses arbitration. When the I

through SDA. The SCL frequency can range from DC to BRGCLK/48.

C Controller Transfers

To initiate a transfer, the master I

slave. The first byte of the message consists of a 7-bit slave port address and a R/W request bit. Note that

C controller's main features:

C BRG takes its input from the BRG clock (BRGCLK), which is

Figure 32-2. I

C Master/Slave General Configuration

C controller is a slave, the SCL clock input shifts data in and out

C controller sends a message specifying a read or write request to an I

MPC885 PowerQUICC Family Reference Manual, Rev. 2

C master/slave configuration is

(EEPROM, for example)

C BRG, shifts receive

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