Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 918

Parallel Interface Port (PIP)
interrupt is generated when the BD finishes processing. Note that a single received data frame can span
several buffers.
For each transfer, the PIP controller generates ACK and BUSY handshake signals on the Centronics
interface. The ACK pulse width and the timing of BUSY with respect to ACK are determined by the timing
parameter register PTPR.
Figure 33-22 shows the PIP configured as a Centronics receiver. The SELECT, PERROR, and FAULT
signals shown are not automatically generated; they are controlled by software and driven on
general-purpose outputs.
33.9.2.1 Centronics Rx Errors and the PIPE
The Centronics receiving error is described in
Error
BD Busy The current BD to be processed is not empty. PIPE[BSY] is flagged. The channel resumes receiving after
user software prepares the BD.
The relevant PIPE event bits for Centronics receiving are CCR, BSY, RCH, and RXB; see
"PIP Event Register (PIPE)."
applies.
33-22
Host
Data[0:7]
STB
ACK
[ * ]
BUSY
[ * ]
SELECT
[ * ]
PERROR
[ * ]
FAULT
[ * ] – Optional
Figure 33-22. PIP as a Centronics Receiver
Table
Table 33-14. Centronics Rx Error
For core-controlled receiving, only the character-based RCH interrupt
MPC885 PowerQUICC Family Reference Manual, Rev. 2
MPC885
(Centronics Device)
PB[16:23]
PB14
PB15
PB31
PB30
PB29
PB28
33-14.
Description
Section 33.4.2,
Freescale Semiconductor