Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 308

System Interface Unit
Note that if the bus monitor is disabled, transfer errors do not cause TEA to be asserted.
10.7 Software Watchdog Timer
The SIU provides the software watchdog timer (SWT) option that prevents system lockup when software
gets trapped in loops without a controlled exit. The software watchdog timer is enabled after HRESET to
automatically generate a HRESET if it times out. If the software watchdog timer is not needed, clear
SYPCR[SWE] to disable it. If it is used, the software watchdog timer requires a special service sequence
to be executed periodically; otherwise, the watchdog timer times out and issues a reset or an NMI, which
is programmed by SYPCR[SWRI]. Once SYPCR is written by the software, SYPCR[SWE] cannot be
changed. See Section 10.4.3, "System Protection Control Register (SYPCR)."
watchdog timer, follow these steps:
1. Write 0x556C to the software service register. (SWSR)
2. Write 0xAA39 to the SWSR.
This sequence clears the watchdog timer and the timing process repeats. If a value other than 0x556C or
0xAA39 is used, the entire sequence must start over. Although the writes must occur in the correct order
before a timeout occurs, any number of instructions may be executed between the writes. This allows
interrupts and exceptions to occur between the two writes when necessary. See
Reset
Not 0x556C/Don't reload
Figure 10-15. Software Watchdog Timer Service State Diagram
The decrementer begins counting when it is loaded with a value from the SWTC field. This value is then
loaded into a 16-bit down-counter clocked by the system clock. When necessary, an additional divide by
2,048 prescaler is used. After the timer reaches 0x0, a software watchdog expiration request is issued to
the reset or NMI control logic. At reset, the value in SWTC is set to the maximum value and is loaded into
the software watchdog down-counter, starting the process.
Although most software disciplines permit or encourage the watchdog concept, some systems require a
selection of timeout periods. For this reason, the software watchdog timer provides a selectable range for
the timeout period. Figure 10-16
into SWTC, the software watchdog timer is not updated until the servicing sequence is written to SWSR.
If the SWE bit is loaded with a zero, the modulus counter will not count.
10-20
0x556C/Don't reload
State 0
Waiting for 0x556C
0xAA39/Reload
Not 0xAA39/Don't reload
shows the method for handling this need. When a new value is loaded
MPC885 PowerQUICC Family Reference Manual, Rev. 2
To service the software
Figure 10-15.
State 1
Waiting for 0xAA39
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