Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 805

Powerquicc family

Table of Contents

Table 29-4. SMC UART-Specific Parameter RAM Memory Map (continued)

Hword Last received break length. Holds the length of the last received break character sequence

Hword Receive break condition counter. Counts break conditions on the line. A break condition may

Hword Break count register (transmit). Determines the number of break characters the UART

R_MASK Hword Temporary bit mask.

From SMC base address. SMC base = IMMR + 0x3E80 (SMC1), 0x3F80 (SMC2).

SMC UART Channel Transmission Process

The UART transmitter is designed to work with almost no intervention from the core. When the core

enables the SMC transmitter, it starts sending idles, which are defined as the full character length of logic

high. The SMC immediately polls the first BD in the transmit channel BD table and once every character

time after that, depending on character length. When there is a message to transmit, the SMC fetches data

from memory and starts sending the message.

When a BD data is completely written to the transmit FIFO, the SMC writes the message status bits into

the BD and clears R. An interrupt is issued if the I bit in the BD is set. If the next TxBD is ready, the data

from its buffer is appended to the previous data and sent over the transmit pin without any gaps between

buffers. If the next TxBD is not ready, the SMC starts sending idles and waits for the next TxBD to be

By appropriately setting the I bit in each BD, interrupts can be generated after each buffer, a specific buffer,

or each block is sent. The SMC then proceeds to the next BD. If the CM bit is set in the TxBD, the R bit

is not cleared, allowing a buffer to be automatically resent next time the CP accesses this buffer. For

instance, if a single TxBD is initialized with the CM and W bits set, the buffer is sent continuously until R

is cleared in the BD.

SMC UART Channel Reception Process

When the core enables the SMC receiver, it enters

then checks the first RxBD to see if it is empty and starts storing characters in the buffer. When the buffer

is full or the MAX_IDL timer expires (if enabled), the SMC clears the E bit in the BD and generates an

interrupt if the I bit in the BD is set. If incoming data exceeds the buffer's length, the SMC fetches the next

BD, and, if it is empty, continues transferring data to this BD's buffer. If CM is set in the RxBD, the E bit

is not cleared, so the CP can overwrite this buffer on its next access.

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measured in character units. For example, if the receive signal is low for 20 bit times and the

defined character length is 10 bits, BRKLN = 0x002, indicating that the break sequence is at

least 2 characters long. BRKLN is accurate to within one character length.

last for hundreds of bit times, yet BRKEC increments only once during that period.

controller sends when the SMC sends a break character sequence after a

command. For 8 data bits, no parity, 1 stop bit, and 1 start bit, each break character is 10

MPC885 PowerQUICC Family Reference Manual, Rev. 2

Serial Management Controllers (SMCs)

mode and waits for the first character. The CP

STOP TRANSMIT