Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 818

Powerquicc family

Table of Contents

Serial Management Controllers (SMCs)

transmission

begins here.

Once SMCMR[REN] is set, the first time-slot after the frame sync causes the SMC receiver to achieve

synchronization. Data is received immediately, but only during defined receive time slots. The receiver

continues receiving data during its defined time slots until REN is cleared. If an

command is issued, the receiver loses synchronization, closes the buffer, and resynchronizes to the first

time slot after the frame sync.

Once SMCMR[TEN] is set, the SMC waits for the transmit FIFO to be loaded before trying to achieve

synchronization. If only a single time slot in a TDM frame is assigned to the SMC, USMC transmission,

as well as reception, is always synchronized to the beginning of that time slot. If multiple time slots in a

TDM frame are assigned to the SMC (as shown in

order of initialization.

When the transmit FIFO is loaded, synchronization and transmission begins depending on the following:

If a buffer is made ready before the SMC is enabled, the first byte is placed in time slot 1 if CLEN

is 8 and to slot 2 if CLEN is greater than 8.

If a buffer is made ready after its SMC is enabled, the first byte can appear in any time slot

associated with this channel.

If a buffer is closed with BD[L] set, then the next buffer can appear in any time slot associated with

this channel.

If SMC runs out of Tx buffers and new ones

are provided later, transmission begins at

the beginning of either time slot.

After REN is set or after

ENTER HUNT MODE

reception begins here.

Figure 29-12. Synchronization with the TSA

MPC885 PowerQUICC Family Reference Manual, Rev. 2

ENTER HUNT MODE

29-12), then synchronization depends on the

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