Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 957

Part VI
Asynchronous Transfer Mode (ATM)
Intended Audience
This part is intended for system designers who need to use the MPC885 asynchronous transfer mode
capabilities. It assumes a basic understanding of the PowerPC exception model, the MPC885 interrupt
structure, the MPC885 communications processor module (CPM) with a particular emphasis on the SCCs,
and a working knowledge of ATM. A complete discussion of these protocols is beyond the scope of this
book.
Contents
This part describes the MPC885 implementation of asynchronous transfer mode (ATM). It contains the
following chapters:
• Chapter 36, "ATM Overview,"
implementation, which adds major new features available in enhanced SAR (ESAR) mode,
including multiple APC priority levels, port-to-port switching, simultaneous MII (100Base-T) and
UTOPIA (half-duplex) capability, relocatable parameter RAM for both SPI and I
UTOPIA both master (ATM side) and slave (PHY side) operation using a split bus
• Chapter 37, "Buffer Descriptors and Connection Tables,"
of the buffer descriptors (BDs) and the transmit and receive connection tables (TCTs and RCTs)
used with ATM.
• Chapter 38, "ATM Parameter RAM,"
SCCs for serial ATM and the UTOPIA interface. The CP also uses parameter RAM to store
operational and temporary values used during SAR activities.
• Chapter 39, "ATM Controller,"
to support connection tables for both single- and multi-PHY interfaces, and the commands
provided to control ATM transmit and receive operations on a channel-by-channel basis.
• Chapter 40, "ATM Pace Control,"
traffic parameters of each channel and defines the multiplex timing for all the channels.
• Chapter 41, "ATM Exceptions,"
event register (SCCE or IDSR1) to provide an interrupt model for ATM operations.
• Chapter 42, "Interface Configuration,"
ATM operations through both the UTOPIA and serial interfaces.
• Chapter 43, "UTOPIA Interface,"
operation, including the UTOPIA modes and the signals provided for UTOPIA support.
Freescale Semiconductor
gives a high-level description of the MPC885 ATM
describes how the parameter RAM is used to configure the
describes the address mapping mechanisms of the ATM controller
describes how the ATM pace control unit (APC) processes
describes how the circular ATM interrupt queue operates with an
describes the programming of registers and parameters for
describes how the MPC885 supports classic SAR MPHY ATM
MPC885 PowerQUICC Family Reference Manual, Rev. 2
2
describes the structure and configuration
C, full-duplex
VI-1