Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 315

Bits Name
13 PIE Periodic interrupt enable
0 Disables the PS bit.
1 Enables the PS bit to generate an interrupt.
14 PITF PIT freeze enable
0 The PIT is unaffected by the FRZ signal.
1 The FRZ signal stops the PIT.
15 PTE Periodic timer enable
0 The PIT is disabled.
1 The PIT is enabled.
10.10.2 PIT Count Register (PITC)
PITC, shown in Figure 10-25, contains a 16-bit value to be loaded into the periodic interrupt down counter.
Note that PITC is a keyed register. It must be unlocked in PITCK before it can be written.
0
Field
Reset
R/W
Addr
Bit
16
Field
Reset
R/W
Addr
This register is not affected by HRESET or SRESET.
Bits Name
0–15 PITC PIT count. Contains the count for the periodic timer. Setting this field to 0xFFFF selects the
maximum count period.
16–31 — Reserved, should be cleared.
Freescale Semiconductor
Table 10-20. PISCR Field Descriptions (continued)
(IMMR & 0xFFFF0000) + 0x244
0000_0000_0000_0000
(IMMR & 0xFFFF0000) + 0x246
Figure 10-25. PIT Count Register (PITC)
Table 10-21. PITC Field Descriptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
PITC
—
R/W
—
R/W
Table 10-21 describes PITC fields.
Description
System Interface Unit
15
31
10-27