Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 209

masked in these areas by clearing (disabling) MSR[ME] for system reset and machine check interrupts and
MSR[EE] for external interrupt, decrementer and two implementation-specific exceptions—debug port
unmaskable interrupt and breakpoint interrupt in nonmaskable mode.
The recoverable exception bit (MSR[RI]) is defined to notify the exception handler code whether it is in a
restartable state. The MSR[RI] shadow bit in SRR1 indicates if the exception is restartable. This bit does
not need to be checked on exception types that are restartable by convention, except those previously
mentioned. When an exception occurs, MSR[RI] is copied to the equivalent bit in SRR1 and cleared. When
an rfi instruction is executed, MSR[RI] is copied from SRR1 or software can change the bit by using it the
mtmsr instruction. The MSR[RI] bit is intended to be set by the exception handler after saving the
machine state, in SRR0 and SRR1 (and DAR and DSISR if needed) and cleared by the exception handler
before retrieving the machine state.
In critical code sections where MSR[EE] is cleared but SRR0 and SRR1 are not busy, MSR[RI] should
remain set. In such cases, if an exception occurs, the process is restartable.
Table 6-18 lists SPRs that facilitate manipulation of MSR[RI] and MSR[EE]. Writing to these locations
performs the specified operation. Attempting to read these locations is treated as an unimplemented
instruction and causes a software emulation exception.
Name SPR MSR[EE]
EIE 80 1
EID 81 0
NRI 82 0
Freescale Semiconductor
Table 6-18. Additional SPRs that Affect MSR Bits
MSR[RI]
1 External interrupt enable:
End of handler's prologue, enable nested external interrupts;
End of critical code segment in which external interrupts were disabled
1 External interrupt disable, but other exception are recoverable:
End of handler's prologue, keep external nested interrupts disabled;
Start of critical code segment in which external interrupts are disabled
0 Nonrecoverable interrupt:
Start of handler's epilogue
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Used For
Exceptions
6-17