Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 691

Table 22-11. SCC UART TxBD Status and Control Field Descriptions (continued)
Bit Name
4 CR Clear-to-send report
0 The next buffer is sent with no delay (assuming it is ready), but if a CTS lost condition occurs,
TxBD[CT] may not be set in the correct TxBD or may not be set at all. Asynchronous flow control,
however, continues to function normally.
1 Normal CTS lost error reporting and three bits of idle are sent between consecutive buffers.
5 A Address. Valid only in multidrop mode—automatic or manual.
0 This buffer contains only data.
1 This buffer contains address characters. All data in this buffer is sent as address characters.
6 CM Continuous mode
0 Normal operation. The CPM clears R after this BD is closed.
1 The CPM does not clear R after this BD is closed, allowing the buffer to be resent next time the
CPM accesses this BD. However, R is cleared by transmission errors, regardless of CM.
7 P Preamble
0 No preamble sequence is sent.
1 Before sending data, the controller sends an idle character consisting of all ones. If the data
length of this BD is zero, only a preamble is sent.
8 NS No stop bit or shaved stop bit sent
0 Normal operation. Stop bits are sent with all characters in this buffer.
1 If PSMR[SYN] = 1, data in this buffer is sent without stop bits. If SYN = 0, the stop bit is shaved,
depending on the DSR setting; see
9–14 — Reserved, should be cleared.
15 CT CTS lost. The CPM writes this status bit after sending the associated buffer.
0 CTS remained asserted during transmission
1 CTS negated during transmission
The data length and buffer pointer fields are described in
22.19 SCC UART Event Register (SCCE) and Mask Register (SCCM)
The SCC event register (SCCE) is used to report events recognized by the UART channel and to generate
interrupts. When an event is recognized, the controller sets the corresponding SCCE bit. Interrupts can be
masked in the UART mask register (SCCM), which has the same format as SCCE. Setting a mask bit
enables the corresponding SCCE interrupt; clearing a bit masks it.
that can be generated by the SCC UART controller.
Freescale Semiconductor
Section 22.14, "Fractional Stop Bits
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Section 21.3, "SCC Buffer Descriptors (BDs)."
Figure 22-10
SCC UART Mode
(Transmitter)."
shows example interrupts
22-19