Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 389

During the data phase of a burst read cycle, the master receives data from the addressed slave. If the master
needs more than one data, it asserts BDIP. When the master receives the next-to-last data, it negates BDIP.
Thus, the slave stops driving new data after receiving the negation of BDIP at the rising clock edge.
In the case of 32-bit port size, the burst includes 4 beats. When the port size is 16 bits and controlled by
the internal memory controller, the burst includes 8 beats. When the port size is 8 bits and controlled by
the internal memory controller, the burst includes 16 beats. The MPC885 bus supports critical data first
access for fixed-size burst. The order of wraparound wraps back to the critical data. For example, assuming
data 2 is critical:
• Case burst of four:
data 2 → data 3 → data 0 → data 1
• Case burst of eight:
data 2 → data 3 → data 4 →......... → data 7 → data 0 → data 1
The following flow, Figure
handshakes for burst read transactions.
Freescale Semiconductor
13-11, and timing diagrams,
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Figure 13-12 through Figure
External Bus Interface
13-15, show the
13-15