Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 202

Exceptions
• Whenever bit 0 of the decrementer changes from 0 to 1, a decrementer exception request is
signaled. If multiple decrementer exception requests are received before the first can be reported,
only one exception is reported.
• If the decrementer is altered by software and if bit 0 is changed from 0 to 1, an exception request
is signaled.
The register settings for the decrementer exception are shown in
Table 6-9. Register Settings after a Decrementer Exception
Register
SRR0 Set to the effective address of the instruction that the processor would have attempted to execute next if
no exception conditions were present.
SRR1 0 Loaded with equivalent bits from the MSR
1–4 Cleared
5–9 Loaded with equivalent bits from the MSR
10–15 Cleared
16–31 Loaded with equivalent bits from the MSR
Note that depending on the implementation, reserved bits in the MSR may not be copied to SRR1.
MSR POW 0
ILE —
EE 0
PR 0
When a decrementer exception is taken, instruction execution resumes at offset 0x00900 from the physical
base address indicated by MSR[IP].
6.1.2.9 System Call Exception (0x00C00)
A system call exception occurs when a System Call (sc) instruction is executed. The effective address of
the instruction following the sc instruction is placed into SRR0. MSR bits are saved in SRR1, as shown in
Table 6-10, and a system call exception is generated.
The system call exception causes the next instruction to be fetched from offset 0x00C00 from the physical
base address indicated by the new setting of MSR[IP]. As with most other exceptions, this exception is
context-synchronizing. Refer to
performed by a context-synchronizing operation.
6-10
Setting Description
FP 0
ME —
SE 0
BE 0
Section 5.2.2.3.1, "Context Synchronization,"
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Table 6-9.
IP — LE
IR 0
DR 0
RI 0
regarding actions
Set to value of ILE
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