Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 783

Powerquicc family

Table of Contents

received. An in-line synchronization pattern or an external synchronization signal can provide bit-level

control of the synchronization process when sending or receiving.

Synchronization in NMSI Mode

The following sections describe synchronization in NMSI mode.

In-Line Synchronization Pattern

The transparent channel can be programmed to receive a synchronization pattern. This pattern is defined

in the data synchronization register, DSR; see

Pattern length is specified in GSMR_H[SYNL], as shown in

SCC Mode Register (GSMR)."

GSMR_H[SYNL] Setting

If a 4-bit SYNC is selected, reception begins as soon as these four bits are received, beginning with the

first bit following the 4-bit SYNC. The transmitter synchronizes on the receiver pattern if

GSMR_H[RSYN] = 1.

Note that the transparent controller does not automatically send the synchronization pattern; therefore, the

synchronization pattern must be included in the transmit buffer.

External Synchronization Signals

If GSMR_H[SYNL] is 0b00, the transmitter uses CTS and the receiver uses CD to begin the sequence.

These signals share two options—pulsing and sampling.

GSMR_H[CDP] and GSMR_H[CTSP] determine whether CD or CTS need to be asserted only once to

begin reception/transmission or whether they must remain asserted for the duration of the transparent

frame. Pulse operation allows an uninterrupted stream of data. However, use envelope mode to identify

frames of transparent data.

The sampling option determines the delay between CD and CTS being asserted and the resulting action by

the SCC. Assume either that these signals are asynchronous to the data and internally synchronized by the

SCC or that they are synchronous to the data with faster operation. This option allows RTS of one SCC to

be connected to CD of another SCC and to have the data synchronized and bit aligned. It is also an option

to link the transmitter synchronization to the receiver synchronization. Diagrams for the pulse/envelope

and sampling options are shown in

Freescale Semiconductor

Section 21.2.3, "Data Synchronization Register (DSR)."

Table 28-1. Receiver SYNC Pattern Lengths of the DSR

An external SYNC signal is used instead of the SYNC pattern in the DSR.

Section 21.4.4, "Controlling SCC Timing with RTS, CTS, and CD."

MPC885 PowerQUICC Family Reference Manual, Rev. 2

28-1. See also

Bit Assignments

SCC Transparent Mode

Section 21.2.1, "General