Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 662

Serial Communications Controllers
Register &
IMMR Offset
SCCE x SCC event register. This 16-bit register reports events recognized by the SCC. When an event is
0xA30 (SCC2) recognized, the SCC sets its corresponding bit in SCCE, regardless of the corresponding mask bit.
0xA50 (SCC3) When the corresponding event occurs, an interrupt is signaled to the CPIC. Bits are cleared by
0xA70 (SCC4) writing ones (writing zeros has no effect). SCCE is cleared at reset, is affected by HRESET and
SRESET, and can be read at any time.
SCCM x SCC mask register. The 16-bit, read/write register allows interrupts to be enabled or disabled using
0xA34 (SCC2) the CPM for specific events in each SCC. An interrupt is generated only if interrupts in the SCC are
0xA54 (SCC3) enabled in the CPIC. If an SCCM bit is zero, the CPM does not proceed with interrupt handling when
0xA74 (SCC4) that event occurs. If an SCCM bit is set, a 1 in the corresponding SCCE bit sets the SCC x event bit
in CIPR. The SCCM and SCCE bit positions are identical. This register is affected by HRESET and
SRESET.
SCCS x SCC status register. This 8-bit, read-only register allows monitoring of the real-time status of RXD.
0xA37 (SCC2) It does not show the real-time status of CTS and CD, which is available in the parallel I/O data
0xA57 (SCC3) registers. Interrupts caused by CTS and CD are described in
0xA77 (SCC4) affected by HRESET and SRESET.
Follow these steps to handle an SCC interrupt:
1. Once an interrupt occurs, read SCCE to determine the interrupt sources and clear those SCCE bits
(in most cases).
2. Process the TxBDs to reuse them if SCCE[TX] or SCCE[TXE] = 1. If the transmit speed is fast or
the interrupt delay is long, the SCC may have sent more than one Tx buffer. Thus, it is important
to check more than one TxBD during interrupt handling. A common practice is to process all
TxBDs in the handler until one is found with its R bit set.
3. Extract data from the RxBD if SCCE[RX], SCCE[RXB], or SCCE[RXF] is set. As with transmit
buffers, if the receive speed is fast or the interrupt delay is long, the SCC may have received more
than one buffer and the handler should check more than one RxBD. A common practice is to
process all RxBDs in the interrupt handler until one is found with its E bit set.
4. Clear CISR[SCCx].
5. Execute the rfi instruction.
21.4.3 SCC Initialization
SCC initialization requires that a number of registers and parameters be configured after a power-on reset.
Regardless of the protocol used, follow these steps:
1. Write the parallel I/O ports to configure and connect the I/O pins to the SCC.
2. Set the SDMA configuration register SDCR[RAID] field to 0b01 (U-bus arbitration priority level
5).
3. Configure the parallel I/O registers to enable RTS, CTS, and CD if these signals are required.
4. If the time-slot assigner (TSA) is used, the serial interface (SI) must be configured. If the SCC is
used in NMSI mode, SICR must still be initialized.
5. Write all GSMR bits except ENT or ENR.
21-16
Table 21-7. SCC x Event, Mask, and Status Registers
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Section 34.4, "Port C." This register is
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