Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 526

PCMCIA Interface
Signal
ALE_x Address latch enable. Output strobes that control the external latches of the address and REG signals
for the appropriate PC card being accessed. ALE_A is asserted when socket A is accessed and ALE_B
is asserted when socket B is accessed. Note that latches are used when power consumption is an issue.
They keep the PCMCIA signals from toggling unnecessarily when the PCMCIA cards are not being
accessed. If power consumption is not an issue, buffers can be used instead of ALE_x signals.
IOIS16_x I/O port is 16 bits. Input. Applies only when the card and its socket are programmed for I/O interface
operation. Must be asserted by the card when the address on the bus corresponds to an address on the
PC card and the I/O port being addressed supports 16-bit accesses. If the I/O region in which the address
resides is programmed as 8 bits wide, IOIS16_x is ignored.
16.2.2 PCMCIA Input Port Signals
The following signals are used by a PCMCIA slot to indicate card status. The MPC885 provides
synchronization, transition detection, optional interrupt generation, and the means for the software to read
the signal state. This function is not necessarily specific to PCMCIA; a system can use these signals as a
general-purpose input port with edge detection and interrupt capability. These signals appear on pins
IP_A[0:7] and IP_B[0:7]. All these signals are symmetrical except IP_x7, which have extended edge
detection capability and IP_x2, which serve as an IOIS16_x cycle-control signals for PCMCIA cycles.
Signal
VS1_x, VS2_x Voltage sense. Input. Used as VS1 and VS2 and generated by PC cards. They notify the socket of
the card V
WP Write protect. Input. When the card and socket are programmed for memory interface operation, this
signal is used as WP. It reflects the state of the write-protect switch on the PC card. The PC card
must assert WP when the card switch is enabled. It must be negated when the switch is disabled.
For a PC card that is writable without a switch, WP must be connected to ground. If the PC card is
permanently write-protected, WP must be connected to V
pins.
CD1_x, CD2_x Card detect. Input. Provide proper detection of card insertion. They must be connected to ground
internally on the PC card, thus, these signals are forced low when a card is placed in the socket.
These signals must be pulled up to system V
socket is powered down. These signals are connected IP_x4 and IP_x3, respectively.
BVD1_x, Battery voltage detect. Input. When the card and its socket are programmed for memory interface
BVD2_x operation, these signals are used as BVD1_x and BVD2_x and are generated by PC cards with
on-board batteries to report the battery condition. Both BVD1_x and BVD2_x must be held asserted
when the battery is in good condition. Negating BVD2_x while keeping BVD1_x asserted indicates
the battery is in a warning condition and should be replaced, although data integrity on the card is
still assured. Negating BVD1_x indicates that the battery is no longer serviceable and data is lost,
regardless of the state of BVD2_x. These signals are connected to IP_x6 and IP_x5, respectively.
STSCHG_x Status change. Input. When the card and its socket are programmed for I/O interface operation,
BVD1_x is used as STSCHG_x and is generated by I/O PC cards. STSCHG_x must be held
negated when the "signal on change" bit and "changed" bit in the card status register on the PC card
are either or both zero. STSCHG_x must be asserted when both bits = 1.
16-4
Table 16-1. PCMCIA Cycle Control Signals (continued)
Table 16-2. PCMCIA Input Port Signals
requirement. These signals are connected to IP_x[0:1].
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MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Description
. These signals are connected to IP_x2
CC
to allow card detection to function while the card
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Freescale Semiconductor