Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 39

Paragraph
Number
44.12 PHY Interface .............................................................................................................. 44-28
44.13 Additional Recommendations...................................................................................... 44-28
45.1 Features .......................................................................................................................... 45-1
45.1.1 FEC Block Diagram................................................................................................... 45-2
45.2 Fast Ethernet Controller Operation................................................................................ 45-3
45.2.1 Transceiver Connection ............................................................................................. 45-3
45.2.2 FEC Frame Transmission .......................................................................................... 45-4
45.2.3 FEC Frame Reception................................................................................................ 45-5
45.2.4 FEC Command Set .................................................................................................... 45-6
45.2.5 Ethernet Address Recognition ................................................................................... 45-6
45.2.6 Hash Table Algorithm................................................................................................ 45-7
45.2.7 Inter-Packet Gap Time ............................................................................................... 45-8
45.2.8 Collision Handling..................................................................................................... 45-8
45.2.9 Internal and External Loopback................................................................................. 45-8
45.2.10 Ethernet Error-Handling Procedure ........................................................................... 45-8
45.2.10.1 Transmission Errors ............................................................................................... 45-9
45.2.10.2 Reception Errors .................................................................................................... 45-9
45.2.11 SDMA Bus Arbitration and Transfers ....................................................................... 45-9
45.2.12 The SDMA Registers............................................................................................... 45-10
45.2.12.1 SDMA Configuration Register (SDCR).............................................................. 45-10
45.3 Programming Model .................................................................................................... 45-10
45.3.1 Communications Processor Timing Register (CPTR) ............................................. 45-11
45.3.2 Parameter RAM ....................................................................................................... 45-12
45.3.2.1 RAM Perfect Match Address Low Register (ADDR_LOW).............................. 45-13
45.3.2.2 RAM Perfect Match Address High (ADDR_HIGH)........................................... 45-14
45.3.2.3 RAM Hash Table High (HASH_TABLE_HIGH) ............................................... 45-14
45.3.2.4 RAM Hash Table Low (HASH_TABLE_LOW)................................................. 45-15
45.3.2.5 Beginning of RxBD Ring (R_DES_START) ...................................................... 45-16
45.3.2.6 Beginning of TxBD Ring (X_DES_START) ...................................................... 45-16
45.3.2.7 Receive Buffer Size Register (R_BUFF_SIZE) .................................................. 45-17
45.3.2.8 Ethernet Control Register (ECNTRL) ................................................................. 45-18
45.3.2.9 Interrupt Event (I_EVENT)/Interrupt Mask Register (I_MASK) ....................... 45-19
45.3.2.10 Ethernet Interrupt Vector Register (IVEC) .......................................................... 45-20
45.3.2.11 RxBD Active Register (R_DES_ACTIVE)......................................................... 45-21
Freescale Semiconductor
Contents
Title
Part VII
Fast Ethernet Controller (FEC)
Chapter 45
Fast Ethernet Controller (FEC)
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Page
Number
xxxix