Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 929

Bits Name
0–13 — Reserved
14 –31 DR n Port B data direction. Configures port B signals as inputs or outputs when functioning as
general-purpose I/O; otherwise, used to select the peripheral function.
0 Select the signal for general-purpose input, or select peripheral function 0.
1 Select the signal for general-purpose output, or select peripheral function 1.
DR14 and DR15 are ignored when port B is used by the PIP controller.
34.3.1.4 Port B Pin Assignment Register (PBPAR)
The port B pin assignment register (PBPAR) configures signals as general-purpose I/O or dedicated for
use with a peripheral.
0 1 2
Field
Reset — — —
R/W
Addr
16 17 18
Field DD16 DD17 DD18 DD19 DD20 DD21 DD22 DD23 DD24 DD25 DD26 DD27 DD28 DD29 DD30 DD31
Reset 0 0 0
R/W R/W R/W R/W
Addr
This register is affected by HRESET but is not affected by SRESET.
Bits Name
0–13 — Reserved
14 –31 DD n Port assignment. Determines whether a signal is configured for general-purpose I/O or
dedicated peripheral function.
0 General-purpose I/O. The peripheral functions of the signal are not used.
1 Dedicated peripheral function. The signal is used by the internal module. The on-chip
34.4 Port C
Port C consists of 12 general-purpose I/O signals that can generate interrupts, which are managed by the
CPM interrupt controller (CPIC).
Freescale Semiconductor
Table 34-9. PBDIR Bit Descriptions
3 4 5 6
— — — —
19 20 21 22
0 0 0 0
R/W R/W R/W R/W
Figure 34-10. Port B Pin Assignment Register (PBPAR)
Table 34-10. PBPAR Bit Descriptions
peripheral function to which it is dedicated can be determined by other bits such as those in
the PBDIR.
Table 34-11 lists port C signal options.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
7 8 9 10
—
— — — —
—
0xABC
23 24 25 26
0 0 0 0
R/W R/W R/W R/W
0xABE
Table 34-10
Description
Parallel I/O Ports
11 12 13 14 15
DD14 DD15
— — — 0
R/W R/W
27 28 29 30 31
0 0 0 0
R/W R/W R/W R/W R/W
describes PBPAR bits.
0
0
34-11