User Connector Descriptions; Port A / Adc (Connector J86, Rv1, J73 And J74) - Freescale Semiconductor MPC5668EVB User Manual

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MPC5668EVB Users Manual Rev 0.1

6. User Connector Descriptions

This section details the pinout of the EVB user connectors. The connectors are 0.1 inch pitch turned pin
headers and are located to the right hand side of the EVB. Pins are grouped by port functionality and the PCB
legend shows the respective port number adjacent to each pin.

6.1.1 Port A / ADC (Connector J86, RV1, J73 and J74)

To provide a quick means of supplying input to the ATD (Analogue To Digital converter), a 2K variable
resistor (RV1) will is connected between P5V and GND, with the output (centre tap) connected to PA0 / AN0
via jumper J86. By removing jumper J86, PA0 is disconnected from the variable resistor and can function as a
normal I/O port. J86 and RV1 are located next to P17.
To allow the EVB core voltages to be monitors by the ATD J74 allows the 2.5v, 3.3v and 5v Switcher and
Linear regulator outputs to be connected to the ATD inputs. J73 allows the 12v EVB supply to be monitored
via resister ladder to reduce the voltage to a level that is in spec of the ATD's range. 65% of the 12v supply is
applied to the ADC via the resistor ladder.
Jumper
Position
J86
FITTED
(RV1)
REMOVED (D)
J73
FITTED
(ADC VSUP)
REMOVED (D)
J74
FITTED
POSN 1-2
REMOVED (D)
J74
FITTED
POSN 3-4
REMOVED (D)
J74
FITTED
POSN 5-6
REMOVED (D)
J74
FITTED
POSN 7-8
REMOVED (D)
Note - PA14 and PA15 can also be used for the EXTAL32 and XTAL32 32Khz reference clock. If these pins
are used for this purpose, they will not be available for GPIO / ADC input.
MPC5668EVBUM/D
Table 6-1. Port A Connector Pinout (P17)
Function
Pin
st
GPIO
1
Alt
1
PA0
AN0
3
PA2
AN2
5
PA4
AN4
7
PA6
AN6
9
PA8
AN8
11
PA10
AN10
13
PA12
AN12
15
PA14
AN14
17
GND
Table 6-2 RV1 Connection Jumper J8
PCB Legend
Page 28 of 29
The user connectors are
located on the right hand
side of the PCB
Function
Pin
st
GPIO
1
Alt
2
PA1
AN1
4
PA3
AN3
6
PA5
AN5
8
PA7
AN7
10
PA9
AN9
12
PA11
AN11
14
PA13
AN13
16
PA15
AN15
18
GND
Description
Output from variable resistor RV1 is applied to PA0
Output from RV1 is not connected to MCU (disabled)
65% of the output from 12v Reg is applied to PA14
12v Reg Output is not connected to PA14
Output from 2.5v Reg is connected to PA10
Output from 2.5v Reg is NOT connected to PA10
Output from 3.3v Reg is connected to PA10
Output from 3.3v Reg is NOT connected to PA10
Output from 5v Switching Reg is connected to PA10
Output from 5v Switching Reg is NOT connected to
PA10
Output from 5v Linear Reg is connected to PA10
Output from 5v Linear Reg is NOT connected to PA10
May 2009

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