Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 339

Table 12-1. MPC885/MPC880 Signal Descriptions (continued)
Hard
Name
Reset
HRESET Low
SRESET Low
XTAL Analog
driving
EXTAL Hi-Z
2
CLKOUT Note
EXTCLK Hi-Z
TEXP High
ALE_A Low
CE1_A High
CE2_A High
WAIT_A Hi-Z
SOC_Split
WAIT_B Hi-Z
IP_A(0) Hi-Z
UTPB_Split[0]
IP_A(1) Hi-Z
UTPB_Split[1]
Freescale Semiconductor
Number Type
B4 Open-drain Hard Reset—Asserting this open drain signal puts the MPC885
in a hard reset state.
A3 Open-drain Soft Reset—Asserting this open drain line puts the MPC885 in a
soft reset state.
A4 Analog This output is one of the connections to an external crystal for the
Output internal oscillator circuitry.
D5 Analog Input This line is one of the connections to an external crystal for the
(3.3 V only) internal oscillator circuitry.
G4 Output Clock Out—This output is the clock system frequency.
A5 Input (3.3 V External Clock—This input is the external input clock from an
only) external source.
C4 Output Timer Expired—This output reflects the status of
PLPRCR[TEXPS].
B7 Output Address Latch Enable A—This output line is asserted when
MPC885 initiates an access to a region under the control of the
PCMCIA interface to socket A.
B15 Output Card Enable 1 Slot A—This output signal enables even byte
transfers when accesses to PCMCIA slot A are handled under the
control of the PCMCIA interface.
C15 Output Card Enable 2 Slot A—This output signal enables odd byte
transfers when accesses to PCMCIA slot A are handled under the
control of the PCMCIA interface.
A2 Input Wait Slot A—This input signal, if asserted low, causes a delay in
the completion of a transaction on the PCMCIA controlled Slot A.
SOC_Split—This input signal is used for the UTOPIA master Rx
start of cell signal in split bus mode only.
C3 Input Wait Slot B—This input, if asserted low, causes a delay in the
completion of a transaction on the PCMCIA controlled Slot B.
B1 Input Input Port A 0—This input signal is monitored by the MPC885 and
its value is reflected in the PIPR and PSCR of the PCMCIA
interface.
UTPB_Split[0]—This input signal is used as Rx data in split bus
mode only. This is the least-significant bit of the UTPB_Aux bus.
C1 Input Input Port A 1—This input signal is monitored by the MPC885 and
its value is reflected in the PIPR and PSCR of the PCMCIA
interface.
UTPB_Split[1]—This input signal is used as Rx data in split bus
mode only.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
External Signals
Description
12-9