Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 402

External Bus Interface
Figure 13-23 shows an example bus arbitration between two contending masters.
CLKOUT
BR0
BG0
BR1
BG1
BB
ADDR/ATTR
TS
TA
The MPC885 can be configured at system reset to use the internal bus arbiter. In this case, the MPC885 is
parked on the bus. Section 10.4.2, "SIU Module Configuration Register (SIUMCR),"
prioritization of external devices relative to the internal MPC885 bus masters. If the external device
requests the bus and the MPC885 does not require it, or the external device has higher priority than the
current internal bus master, the MPC885 grants the bus to the external device.
internal finite state machine that implements the arbiter protocol.
13-28
Master 0
'turns on'
and
drives
signals
Figure 13-23. Bus Arbitration Timing Diagram
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Master 0 Master 1
negates 'turns on'
BB and
and drives
'turns off' signals
Figure 13-24
describes
shows the
Freescale Semiconductor