Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 535

Bits Name
27 CB_ERDY_F
28–31 —
PCMCIA Interface General Control Register (PGCR x )
16.4.4
PGCRA or PGCRB, shown in
external latches, and specify the source used for a DMA request.
0
Field
Reset
R/W
Addr
16 17 18
Field CxDREQ
Reset
R/W
Addr
Figure 16-6. PCMCIA Interface General Control Register (PGCRx)
This register is affected by HRESET but is not affected by SRESET.
Bits Name
0–7 CxIREQLVL
8–15 CxSCHLVL
16–17 CxDREQ
18–23 —
24 CxOE
25 CxRESET
26–31 —
Freescale Semiconductor
Table 16-10. PER Field Descriptions (continued)
Enable for RDY/IRQ card B pin falling edge detected
Reserved, should be 0.
Figure 16-6, are used to reset the PCMCIA cards, disable the output of the
7
CxIREQLVL
0000_0000_0000_0000
(IMMR & 0xFFFF0000) + 0x0E0 (PGCRA); 0x0E4 (PGCRB)
23
—
0000_0000_0000_0000
(IMMR & 0xFFFF0000) + 0x0E2 (PGCRA); 0x0E6 (PGCRB)
Table 16-11. PGCRx Field Descriptions
Card x IREQ_x interrupt level. Only one bit of this field should be set at any time.
Card x STSCHG_x interrupt level. Only one CASCHLVLx bit should be set at any time.
Card x DREQ. Defines internal DMA request for the on-chip DMA controller (CADREQ
controls DMA channel 0. CBDREQ controls DMA channel 1).
0x Disable internal DMA request from slot x.
10 Enable IOIS16_x as internal DMA request for slot x.
11 Enable SPKR_x as internal DMA request for slot x.
Reserved, should be cleared.
Card x output enable. CAOE is reflected on OP1 and CBOE is reflected on OP2 used
to three-state the external buffers when the card's power is activated.
Card x reset. CARESET is reflected on OP0 used to reset card A. CBRESET is reflected
on OP3 used to reset card B.
Reserved, should be cleared.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
8
CxSCHLVL
R/W
24 25 26
CxOE CxRESET
R/W
Table 16-11
Description
PCMCIA Interface
15
31
—
describes PGCRx fields.
16-13