Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 356

External Signals
12.2.2 MPC875/MPC870 System Bus Signals
The MPC875 system bus consists of signals that interface with the external bus. Many of these signals
perform different functions, depending on how the user assigns them. The input and output signals in
Table 12-2 are identified by their abbreviations.
Hard
Name
Reset
A[0:31] Hi-Z
TSIZ0 Hi-Z
REG
TSIZ1 Hi-Z
RD/WR Hi-Z
BURST Hi-Z
BDIP See
GPL_B5 Table 12-3
TS Hi-Z
12-26
Table 12-2. MPC875/MPC870 Signal Descriptions
Number Type
See Bidirectional Address Bus—Provides the address for the current bus cycle. A0
Figure 12-4 three-state is the msb. The bus is output when an internal master starts a
transaction on the external bus. The bus is input when an external
master starts a transaction on the bus.
F16 Bidirectional Transfer Size 0—When accessing a slave in the external bus,
three-state used (together with TSIZ1) by the bus master to indicate the
number of operand bytes waiting to be transferred in the current
bus cycle. TSIZ0 is an input when an external master starts a bus
transaction.
Register—When an internal master initiates an access to a slave
controlled by the PCMCIA interface, REG is output to indicate
which space in the PCMCIA card is accessed.
G14 Bidirectional Transfer Size 1—Used (with TSIZ0) by the bus master to indicate
three-state the number of operand bytes waiting to be transferred in the
current bus cycle. The MPC875 drives TSIZ1 when it is bus
master. TSIZ1 is input when an external master starts a bus
transaction.
D13 Bidirectional Read/Write—Driven by a bus master to indicate the direction of
three-state the data transfer. A logic one indicates a read from a slave device
and a logic zero indicates a write to a slave device.
The MPC875 drives this signal when it is bus master. Input when
an external master initiates a transaction on the bus.
B9 Bidirectional Burst Transaction—Driven by the bus master to indicate that the
three-state current initiated transfer is a burst. The MPC875 drives this signal
when it is bus master. This signal is input when an external master
initiates a transaction on the bus.
C13 Output Burst Data in Progress—When accessing a slave device in the
external bus, the master on the bus asserts this signal to indicate
that the data beat in front of the current one is the one requested
by the master. BDIP is negated before the expected last data beat
of the burst transfer.
General-Purpose Line B5—Used by the memory controller when
UPMB takes control of the slave access.
C11 Bidirectional Transfer Start—Asserted by a bus master to indicate the start of a
active bus cycle that transfers data to or from a slave device.
pull-up Driven by the master only when it has gained the ownership of the
bus. Every master should negate this signal before the bus
relinquish. TS requires the use of an external pull-up resistor.
The MPC875 samples TS when it is not the external bus master
to allow the memory controller/PCMCIA interface to control the
accessed slave device. It indicates that an external synchronous
master initiated a transaction.
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Freescale Semiconductor