Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 949

SMCEx 3
BRK
• • •
The following procedure prevents possible interrupt errors when modifying mask registers, such as the
CIMR, SCCM, SMCM, or any other CPM interrupt mask:
1. Clear MSR[EE]. (Disable external interrupts to the core.)
2. Modify the mask register.
3. Set MSR[EE]. (Enable external interrupts to the core.)
This mask modification procedure ensures that an already pending interrupt is not masked before being
serviced. Masking a pending interrupt causes the interrupt error vector (see
other valid CPM interrupts are pending. (The error vector cannot be masked.)
35.4 Generating and Calculating Interrupt Vectors
Unmasked CPM interrupts are presented to the core in order of priority. The core responds to an interrupt
request by setting CIVR[IACK]. The CPIC passes the five low-order bits of the vector corresponding to
the highest priority, unmasked, pending CPM interrupt in CIVR[VN]. These encodings are shown in
Table 35-2.
Interrupt
Source Description
Number
0x1F Parallel I/O–PC15
0x1E
0x1D
0x1C
0x1B
Freescale Semiconductor
4 5 6 7
– BSY TX RX
SMCx Interrupt to CPIC
Figure 35-2. Interrupt Request Masking
Table 35-2. Interrupt Vector Encodings
CIVR[0–4]
11111
USB 11110
SCC2 11101
SCC3 11100
SCC4 11011
MPC885 PowerQUICC Family Reference Manual, Rev. 2
SMCMx 3 4 5
BRK – BSY
• • •
Table
Interrupt
Source Description
Number
0x0F Parallel I/O—PC11
0x0E Parallel I/O—PC10
0x0D Reserved
0x0C
0x0B Parallel I/O—PC9
CPM Interrupt Controller
6 7
TX RX
35-2) to be issued if no
CIVR[0–4]
01111
01110
01101
Timer 3 01100
01011
35-5