Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 908

Parallel Interface Port (PIP)
• Port B open-drain register. Configures the data signals PBDAT[16–31] as normal or wired-OR. See
Section 34.3.1.1, "Port B Open-Drain Register (PBODR)."
33.5 PIP Buffer Descriptors
The CP uses PIP receive and transmit buffer descriptors to manage the specific transfer of each buffer.
Each 64-bit buffer descriptor has the following structure:
• The half word at offset + 0 contains status and control bits.
• The half word at offset + 2 contains the data length (in bytes) that is sent or received.
— For an RxBD, this is the number of octets the CP writes into this RxBD's buffer once the
descriptor closes. The controller writes this field after the received data is placed into the
associated buffer. Memory allocated for this buffer should be no smaller than MRBLR.
— For a TxBD, this is the number of octets the CP should transmit from its buffer. However, it is
never modified by the CP. This value should be greater than zero. For an 8-bit PIP, this value
can be odd or even; for a 16-bit PIP, it must be even.
• The word at offset + 4 points to the beginning of the buffer.
— For an RxBD, the value must be even and can reside in internal or external memory.
— For a TxBD, this pointer can be even or odd, unless the port size exceeds 8 bits, for which it
must be even. The buffer can reside in internal or external memory.
33.5.1 The PIP Tx Buffer Descriptor (TxBD)
The CP uses buffer descriptors (TxBDs) to confirm buffer transmission and indicate error conditions to
the core. Figure 33-9 shows the PIP TxBD.
Bit
0 1
Offset + 0 R —
Offset + 2
Offset + 4
Offset + 6
Table 33-9 describes the PIP Tx buffer descriptor status and control field. The data length and buffer
pointer are described in
Table 33-9. PIP TxBD Status and Control Field Descriptions
Bits Name
0 R Ready. If PIP tries to transmit a buffer that is not ready, PIPE[TXE] is flagged.
0 The buffer associated with this descriptor is not ready for transmission. This descriptor and its
buffer can be updated. The CP clears R after the buffer is sent or an error is encountered.
1 The buffer is ready for sending or is being sent. No fields of this BD can be written while R = 1.
1 — Reserved, should be cleared.
33-12
2 3 4 5
W I L — CM
Figure 33-9. PIP Tx Buffer Descriptor (TxBD)
Section 33.5, "PIP Buffer Descriptors,"
MPC885 PowerQUICC Family Reference Manual, Rev. 2
6 7
—
Data Length
Tx Buffer Pointer
above.
Description
11 12 13 14 15
F PE S —
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