Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 713

Powerquicc family

Table of Contents

The HDLC bus differs from the I.430 and T1.605 standards as follows:

The HDLC bus uses a separate input signal rather than the echo bit to monitor data; the transmitted

data is simply connected to the CTS input.

The HDLC bus is a synchronous, digital open-drain connection for short-distance configurations,

rather than the more complex S/T interface.

Any HDLC-based frame protocol can be used at layer 2, not just LAPD.

HDLC bus devices wait 8–10 rather than 7–10 bit times before transmitting. (HDLC bus has only

The collision-detection mechanism supports only:

NRZ-encoded data

A common synchronous clock for all receivers and transmitters

Non-inverted data (GSMR[RINV, TINV] = 0)

Open-drain connection with no external transceivers

Figure 23-10

shows the most common HDLC bus LAN configuration, a multimaster configuration. A

station can transfer data to or from any other LAN station. Transmissions are half-duplex, which is typical

1. Transceivers may be used to extend the LAN size.

2. The TXD pins of slave devices should be configured to open-drain in the port C parallel I/O port.

3. Clock is a common RCLK/TCLK for all stations.

Figure 23-10. Typical HDLC Bus Multimaster Configuration

In single-master configuration, a master station transmits to any slave station without collisions. Slaves

communicate only with the master, but can experience collisions in their access over the bus. In this

configuration, a slave that communicates with another slave must first transmit its data to the master, where

the data is buffered in RAM and then resent to the other slave. The benefit of this configuration, however,

is that full-duplex operation can be obtained. In a point-to-multipoint environment, this is the preferred

configuration.

Figure 23-11

Freescale Semiconductor

HDLC Bus LAN

shows the single-master configuration.

MPC885 PowerQUICC Family Reference Manual, Rev. 2

SCC HDLC Mode