Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 926

Parallel I/O Ports
Signal
PBPAR[DD n ]
= 0
PB31 Port B31
PB30 Port B30
PB29 Port B29
PB28 Port B28
PB27 Port B27
PB26 Port B26
PB25 Port B25
PB24 Port B24
PB23 Port B23
PB22 Port B22
PB21 Port B21
PB20 Port B20
PB19 Port B19
PB18 Port B18
PB17 Port B17
PB16 Port B16
PB15 Port B15
PB14 Port B14
1
UT = PDPAR[UT]
2
In Slave Mode, the UTOPIA signals are named from the UTOPIA Master's perspective.
34-8
Table 34-6. Port B Pin Assignment
Signal Function
PBPAR[DD n ] = 1
PBDIR[DR n ] = 0
UT = 1
UTOPIA
1
UT = 0 Master
(Muxed or
Split)
MII-TXCLK
RMII1-REFCLK
—
—
BRGO4
BRGO1
BRGO2
SMTXD1 RxAddr[3]
SMRXD1 TxAddr[3]
SMSYN1 TxAddr[2]
SMSYN2 TxAddr[4]
SMTXD2 TxAddr[1]
SMRXD2 TxAddr[0]
MII1-RXD3
L1ST2 RxAddr[4]
L1ST3 RxAddr[1]
L1ST4 RxAddr[0]
– TxClav
– RxAddr[2]
MPC885 PowerQUICC Family Reference Manual, Rev. 2
PBDIR[DR n ] = 1
UT = 1
UTOPIA
UT = 0
2
Slave (Split
Only)
SPISEL
SPICLK
SPIMOSI
SPIMISO
I2CSDA
I2CSCL
— TxAddr[3]
— RxAddr[3]
SDACK1 RxAddr[2]
SDACK2 RxAddr[4]
BRG01 RxAddr[1]
L1CLKOA RxAddr[0]
RTS4
RTS2 TxAddr[4]
BRG02 TxAddr[1]
RTS4/L1RQa TxAddr[0]
BRG03 RxClav
TxAddr[2]
Input to On-chip
Peripherals
(Default)
V
DD
SPICLK = GND
SPIMOSI = V
DD
SPIMISO = SPIMOSI
I2CSDA = V
DD
I2CSCL = GND
—
SMRXD1 = GND
SMSYN1 = GND
SMSYN2 = GND
—
SMRXD2 = GND
MII1-RXD3 = GND
—
—
—
—
—
Freescale Semiconductor