Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 142

The MPC8xx Core
3.2 PowerPC Architecture Overview
The PowerPC architecture takes advantage of recent technological advances in such areas as process
technology, compiler design, and reduced instruction set computing (RISC) microprocessor design to
provide software compatibility across a diverse family of implementations, primarily single-chip
microprocessors, intended for a wide range of systems, including battery-powered personal computers;
embedded controllers; high-end scientific and graphics workstations; and multiprocessing,
microprocessor-based mainframes.
To provide a single architecture for such a broad assortment of processor environments, the PowerPC
architecture is both flexible and scalable.
The flexibility of the PowerPC architecture offers many price/performance options. Designers can choose
whether to implement architecturally defined features in hardware or in software. For example, a processor
designed for a high-end workstation has greater need for the performance gained from implementing
floating-point normalization and denormalization in hardware than a device using a PowerPC-embedded
controller might.
The PowerPC architecture defines the following features:
• Separate 32-entry register files for integer instructions. The general-purpose registers (GPRs) hold
source data for integer arithmetic instructions.
• Instructions for loading and storing data between the memory system and the GPRs
• Uniform-length instructions to allow simplified instruction pipelining and parallel processing
instruction dispatch mechanisms
• Nondestructive use of registers for arithmetic instructions in which the second, third, and
sometimes the fourth operand, typically specify source registers for calculations whose results are
usually stored in the target register specified by the first operand
• A precise exception model
• A flexible architecture definition that allows certain features to be performed in either hardware or
with assistance from implementation-specific software depending on the needs of the processor
design
• User-level instructions for explicitly storing, flushing, and invalidating data in the on-chip caches.
The architecture also defines special instructions (cache block touch instructions) for speculatively
loading data before it is needed, reducing the effect of memory latency.
• A memory model that allows weakly-ordered memory accesses. This allows bus operations to be
reordered dynamically, which improves overall performance and in particular reduces the effect of
memory latency on instruction throughput.
• Support for separate instruction and data caches (Harvard architecture) and for unified caches
• Support for both big- and little-endian addressing modes
• Support for 64-bit addressing. The architecture supports both 32- or 64-bit implementations. This
document describes the 32-bit portion of the PowerPC architecture. For information about the
64-bit architecture, see Programming Environments Manual for Implementations of the PowerPC
Architecture.
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MPC885 PowerQUICC Family Reference Manual, Rev. 2
Freescale Semiconductor