Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 839

0
Field —
Reset
R/W
Addr
These registers are affected by HRESET and SRESET.
Bits Name
0–1 — Reserved, should be cleared.
2 MME Multimaster error. Set when SPISEL is asserted externally while the SPI is in master mode.
3 TXE Tx error. Set when an error occurs during transmission.
4 — Reserved, should be cleared.
5 BSY Busy. Set after the first character is received but discarded because no Rx buffer is available.
6 TXB Tx buffer. Set when the Tx data of the last character in the buffer is written to the Tx FIFO. Wait two
character times to be sure data is completely sent over the transmit signal.
7 RXB Rx buffer. Set after the last character is written to the Rx buffer and the BD is closed.
30.4.3 SPI Command Register (SPCOM)
The SPI command register (SPCOM), shown in
0
Field STR
Reset 0
R/W
Addr
This register is affected by HRESET and SRESET.
Bits Name
0 STR Start transmit. For an SPI master, setting STR causes the SPI to start transferring data to and from
the Tx/Rx buffers if they are prepared. For a slave, setting STR when the SPI is idle causes it to load
the Tx data register from the SPI Tx buffer and start sending with the next SPICLK after SPISEL is
asserted. STR is cleared automatically after one system clock cycle.
1–7 — Reserved and should be cleared.
Freescale Semiconductor
1 2 3
MME TXE
0xAA6 (SPIE); 0xAAA (SPIM)
Figure 30-7. SPI Event/Mask Registers (SPIE/SPIM)
Table 30-3. SPIE/SPIM Field Descriptions
Figure
1
Figure 30-8. SPI Command Register (SPCOM)
Table 30-4. SPCOM Field Descriptions
MPC885 PowerQUICC Family Reference Manual, Rev. 2
4 5
— BSY
0
R/W
Table 30-3 describes the SPIE/SPIM fields.
Description
30-8, is used to start SPI operation.
—
0
R/W
0xAAD
Table 30-4 describes the SPCOM fields.
Description
Serial Peripheral Interface (SPI)
6 7
TXB RXB
7
30-9