Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 190

MPC885 Instruction Set
Note that when data address translation is disabled (MSR[DR] = 0), the Data Cache Block Set to Zero
(dcbz) instruction allocates a cache block in the cache and may not verify that the physical address is valid.
If a cache block is created for an invalid physical address, a machine check condition may result when an
attempt is made to write that cache block back to memory. The cache block could be written back as a
result of the execution of an instruction that causes a cache miss and the invalid addressed cache block is
the target for replacement or a Data Cache Block Store (dcbst) instruction.
Table 5-19 lists the cache instructions that are accessible to user-level programs.
Name
Data Cache Block Touch
Data Cache Block Touch for
Store
Data Cache Block Set to Zero dcbz
Data Cache Block Store
Data Cache Block Flush
Instruction Cache Block
Invalidate
5.2.6 PowerPC OEA Instructions
The PowerPC OEA includes the structure of the memory management model, supervisor-level registers,
and the exception model.
5.2.6.1 System Linkage Instructions
This section describes system linkage instructions (see
instruction that permits a user program to call on the system to perform a service and causes the processor
to take an exception. The Return from Interrupt (rfi) instruction is a supervisor-level instruction that is
useful for returning from an exception handler.
Name
System Call
Return from Interrupt
5.2.6.2 Processor Control Instructions—OEA
Processor control instructions read from and write to the condition register (CR), machine state register
(MSR), and special-purpose registers (SPRs), and to read from the time base register (TBU or TBL).
5-20
Table 5-19. User-Level Cache Instructions
Mnemonic Syntax
dcbt rA,rB The appropriate cache block is checked for a hit. If it is a miss,
the instruction is treated as a regular miss, except that bus
dcbtst rA,rB
error does not cause an exception. If no error occurs, the
cache is updated.
rA,rB Executes as defined in the VEA.
dcbst rA,rB Executes as defined in the VEA.
dcbf rA,rB Executes as defined in the VEA.
icbi rA,rB The MMU translates the EA and the associated instruction
cache block is invalidated if hit.
Table 5-20. System Linkage Instructions
sc
rfi
MPC885 PowerQUICC Family Reference Manual, Rev. 2
MPC885 Notes
Table 5-20). The sc instruction is a user-level
Mnemonic Syntax
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