Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 599

interrupt) behavior is independent of the L bit—the user may disable individual BD interrupts (and/or
mask them) for multi-buffer chains.
19.3.5 IDMA CP Commands
The core issues the following IDMA commands to the CP:
• —The CPM resets the IDMA internal state. The current BD pointer is reset to the top of
INIT IDMA
the BD table (IBASE).
• —The CP terminates current IDMA transfers. IDSR[DONE] is set, and the current BD
STOP IDMA
is closed. If the destination is memory, the IDMA internal storage buffer is transferred before
termination, regardless of the source. If the destination is a peripheral, the internal storage buffer
is flushed and the transfer terminated without writing to the peripheral. At the next request, the next
BD in the table is processed.
See Section 18.6.3, "CP Command Register (CPCR),"
19.3.6 IDMA Channel Operation
An IDMA channel operation consists of the following events—IDMA channel initialization, data transfer,
and block termination. In the initialization phase, the core loads the global IDMA channel information into
the IDMA parameter RAM, builds the IDMA BD table, and starts the channel. In the transfer phase, the
CPM accepts a transfer request, reads the transfer-specific information from the current BD into the IDMA
parameter RAM, programs the physical SDMA channel, and provides addressing and bus control. The
termination phase begins when the transfer byte count reaches zero (or a bus error occurs). The CPM then
interrupts the core (unless masked), and the current BD pointer moves to the next BD in the table.
To begin a block transfer, initialize the IDMA registers, and build the IDMA BDs with information
describing the data block, device type, and other special control options. See
Parameter RAM," and Section 19.3.5, "IDMA CP Commands."
19.3.6.1 Activating an IDMA Channel
IDMA requests are generated externally via the DREQ signals. (There is no mechanism for generating
internal IDMA requests.) After initializing the IDMA parameter RAM and the BD table, enable the DREQ
signal by setting the corresponding PCSO[DREQ] of the port C special options register; see
Section 34.4.1.4, "Port C Special Options Register (PCSO)."
activates the corresponding IDMA channel. Requests for IDMA1 have priority over IDMA2.
19.3.6.2 Suspending an IDMA Channel
Disabling the corresponding DREQ signal by clearing the corresponding PCSO[DREQ] suspends the
IDMA channel transfer. A transfer in progress will be completed before the bus is released. No further bus
cycles are started while PCSO[DREQ] remains cleared. During channel suspension, the core can access
IDMA internal registers to determine the status of the channel or to alter parameters. If PCSO[DREQ] is
set again while a transfer request is pending, the channel arbitrates for the bus and continues normal
operation.
Freescale Semiconductor
MPC885 PowerQUICC Family Reference Manual, Rev. 2
SDMA Channels and IDMA Emulation
for the mechanics of issuing CP commands.
Section 19.3.2, "IDMA
Enabling the DREQ signal effectively
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