Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 120

Memory Map
Table 2-1. MPC885 Internal Memory Map (IMMR[14–15]=00) (continued)
Offset
0A0 PBR4—PCMCIA interface base register 4
0A4 POR4—PCMCIA interface option register 4
0A8 PBR5—PCMCIA interface base register 5
0AC POR5—PCMCIA interface option register 5
0B0 PBR6—PCMCIA interface base register 6
0B4 POR6—PCMCIA interface option register 6
0B8 PBR7—PCMCIA interface base register 7
0BC POR7—PCMCIA interface option register 7
0C0–0DF Reserved
0E0 PGCRA—PCMCIA interface general control register
A
0E4 PGCRB—PCMCIA interface general control register
B
0E8 PSCR—PCMCIA interface status changed register
0EC–0EF Reserved
0F0 PIPR—PCMCIA interface input pins register
0F4–0F7 Reserved
0F8 PER—PCMCIA interface enable register
0FC–0FF Reserved
100 BR0—Base register bank 0
104 OR0—Option register bank 0
108 BR1—Base register bank 1
10C OR1—Option register bank 1
110 BR2—Base register bank 2
114 OR2—Option register bank 2
118 BR3—Base register bank 3
11C OR3—Option register bank 3
120 BR4—Base register bank 4
124 OR4—Option register bank 4
128 BR5—Base register bank 5
12C OR5—Option register bank 5
130 BR6—Base register bank 6
2-2
Name
Memory Controller
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Size Section/Page
32 bits 16.4.5/16-14
32 bits 16.4.6/16-14
32 bits 16.4.5/16-14
32 bits 16.4.6/16-14
32 bits 16.4.5/16-14
32 bits 16.4.6/16-14
32 bits 16.4.5/16-14
32 bits 16.4.6/16-14
32 bytes —
32 bits 16.4.4/16-13
32 bits 16.4.4/16-13
32 bits 16.4.2/16-10
4 bytes —
32 bits 16.4.1/16-8
4 bytes —
32 bits 16.4.3/16-11
4 bytes —
32 bits 15.4.1/15-8
32 bits 15.4.2/15-11
32 bits 15.4.1/15-8
32 bits 15.4.2/15-11
32 bits 15.4.1/15-8
32 bits 15.4.2/15-11
32 bits 15.4.1/15-8
32 bits 15.4.2/15-11
32 bits 15.4.1/15-8
32 bits 15.4.2/15-11
32 bits 15.4.1/15-8
32 bits 15.4.2/15-11
32 bits 15.4.1/15-8
Freescale Semiconductor