Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 194

Exceptions
previous instructions have completed. If a late error occurs, a store cycle (or a nonspeculative load cycle)
can be issued and aborted.
In each exception handler, when registers SRR0 and SRR1 are saved, MSR[RI] can be set.
Table 6-1 defines the offset value by exception type and the sections that follow describe each exception
in detail. Note that the base is determined by the setting of MSR[IP].
Offset Exception
0x00000 Reserved
0x00100 System reset interrupt
0x00200 Machine check interrupt
0x00300 DSI
0x00400 ISI
0x00500 External interrupt
0x00600 Alignment
0x00700 Program
0x00800 Floating-point unavailable
0x00900 Decrementer
0x00A00– Reserved
0x00B00
0x00C00 System call
0x00D00 Trace
0x00E00 Floating-point assist
6-2
Table 6-1. Offset of First Instruction by Exception Type
OEA-Defined Exceptions
—
See Section 6.1.2.1, "System Reset Interrupt (0x00100)."
See Section 6.1.2.2, "Machine Check Interrupt (0x00200)."
A DSI exception is never generated by hardware, but software may branch to
this location because of an data TLB error or miss exception. See
Section 6.1.2.3, "DSI Exception (0x00300)."
An ISI exception is never generated by the hardware, but software may
branch to this location because of an implementation-specific instruction TLB
error exception. See
See Section 6.1.2.5, "External Interrupt Exception (0x00500)."
Alignment exceptions result from the following conditions:
• The operand of a load/store multiple is not word-aligned.
• The operand of a lwarx or stwcx. is not word-aligned.
• The operand of a load/store instruction is not naturally aligned when
MSR[LE] = 1.
• Trying to execute a multiple/string instruction when MSR[LE] = 1.
See Section 6.1.2.3, "DSI Exception (0x00300)."
The MPC885 cannot generate a floating-point exception type exception. See
Section 6.1.2.7, "Program Exception (0x00700)."
software emulation exception is generated instead of an illegal instruction
type program exception. A privileged instruction program exception is
generated for an on-core valid SPR field or any SPR encoded as an external
SPR if SPR[0] = 1 and MSR[PR] = 1, as well as for attempts to execute
supervisor-level instructions when MSR[PR] = 1. See
The MPC885 cannot generate a floating-point exception. Attempting to
execute a floating-point instruction causes an implementation-specific
software emulation exception (see
Exception (0x01000)") regardless of the setting of MSR[FP].
See Section 6.1.2.8, "Decrementer Exception (0x00900)."
—
See Section 6.1.2.9, "System Call Exception (0x00C00)."
See Section 6.1.2.10, "Trace Exception (0x00D00)."
See Section 6.1.2.11, "Floating-Point Assist Exception."
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Description
Section 6.1.2.4, "ISI Exception (0x00400)."
An implementation-specific
Section 6.1.3.1, "Software Emulation
Table 6-11.
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