Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 626

Serial Interface
Figure 20-16 and Figure 20-17
sync delay of one bit.
CE=1
L1CLK
L1SYNC
L1SYNC
L1TxD
(Bit-0)
L1ST
(On Bit-0)
Figure 20-16. Falling Edge (FE) Effect When CE = 1 and x FSD = 01
CE=0
L1CLK
L1SYNC
L1SYNC
L1TXD
(Bit-0)
L1ST
(On Bit-0)
Figure 20-17. Falling Edge (FE) Effect When CE = 0 and x FSD = 01
20-20
show example timings while varying SIMODE[CE] with a constant frame
MPC885 PowerQUICC Family Reference Manual, Rev. 2
L1ST Driven from Clock High for Both FE Settings
Rx Sampled Here
L1ST is Driven from Clock Low
in Both the FE Settings
Rx Sampled Here
xFSD=01
(FE=0)
(FE=1)
xFSD=01
(FE=0)
(FE=1)
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