Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 421

Digital implementation of frequency control and loop filtering functions in the design of the DPLL allows
the following new features:
• Eliminating an on-board loop filter capacitor, minimization of internal capacitor value;
• Selection of frequency and phase/frequency operation modes;
• An improved noise immunity, eliminating additional supply and ground pins;
• A high frequency resolution with a reduced lock time;
• Reduced sensitivity to parameter variations caused by temperature and process.
The main purpose of the DPLL is to generate a stable reference frequency by multiplying the frequency
and eliminating the clock skew. The DPLL allows the processor to operate at a high internal clock
frequency using a low frequency clock input, providing two advantages. First, lower frequency clock input
reduces the overall electromagnetic interference generated by the system. Second, the programmability of
the oscillator enables the system to operate at a variety of frequencies with only a single external clock
source.
The DPLL reference clock (OSCLK) can be generated from either of the external clock sources described
in Section 14.2.1, "External Reference Clocks."
Inside the DPLL, the OSCLK is divided by the predivision factor (PDF+1) to generate DPDREF clock.
Frequency range of DPDREF is 10 to 32 Mhz. This DPDREF clock is used, further inside the DPLL, for
generating the output clock of the DPLL, i.e DPGDCK (see
is 160 to 320 Mhz. These frequency ranges must be maintained by both the reset configuration settings of
the DPLL and Interface and the final operating frequency of the DPLL and the Interface.
The interface logic works in three modes depending on divider selection input PLPRCR[S]. The formula
for the output frequency of the DPLL and interface logic for each mode is given as per formula.
jdbck = 2 *
For synchronization between EXTCLK to CLKOUT, the total value that the
EXTCLK gets multiplied by must be an integer.
This also requires the total MF factor i.e [MFI + (MFN/(MFD+1))] to be an
integer as a prerequisite.
Table 14-2 shows the DPLL parameters for some typical system frequencies during Normal Operation.
The frequency after Power On Reset is shown in
for the integer part (MFI), the numerator part (MFN), the denominator part minus 1(MFD), and the
predivison factor minus 1 (PDF) with their ranges listed in
MFI+(MFN/(MFD+1)), must be between 5 to 15.
Freescale Semiconductor
MFI + (MFN/(MFD+1))
PDF + 1
for S = 0, 1, or 2
NOTE
Table
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Figure 14-1). Frequency range of DPGDCK
s
* OSCLK / 2
14-3. The multiplication factors (MF) shown are
Table 14-9. The total MF value,
Clocks and Power Control
14-5