Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 221

For data array (IC_ADR[17] = 1) read commands, the word selected by IC_ADR[28–29] is placed in the
target general-purpose register. For tag array (IC_ADR[17] = 0) read commands, the tag and state
information is placed in the target general-purpose register.
register for a tag read.
Table 7-6. IC_DAT Format for a Tag Read (IC_ADR[17] = 0)
0–19 20–21
Tag value Reserved 0 = Invalid
7.3.1.2 IC_CST Commands
All IC_CST commands, except the load-and-lock cache block command, are executed immediately after
writing to the IC_CST register and do not generate any errors. Therefore, when executing these commands
there is no need to check the error type bits in the IC_CST register. All commands should be followed by
an isync instruction, if the instruction cache command is required to affect all instruction fetches that come
after it in the program order. In addition, correct operation of the instruction cache relies on software
following the procedures described in
Note that when the instruction cache is executing a command, it stops handling CPU requests, which can
result in machine stalls.
7.3.1.2.1 Instruction Cache Enable/Disable Commands
The instruction cache enable command (IC_CST[CMD] = 0b001) is used to enable the instruction cache;
the instruction cache disable command (IC_CST[CMD] = 0b010) is used to disable the instruction cache.
Neither of these commands has any error cases. The current state of the instruction cache is available by
reading the instruction cache enable status bit (IC_CST[IEN]).
When disabled, the MPC885 ignores the instruction cache valid bit and operates as if all accesses have
caching-inhibited access attributes (that is, all instruction fetches are propagated to the bus as single-beat
transactions). Disabling the instruction cache does not affect the instruction address translation logic;
MSR[IR] controls instruction address translation.
At hard reset, the instruction cache is disabled.
7.3.1.2.2 Instruction Cache Load-and-Lock Cache Block Command
The instruction cache load and lock cache block command (IC_CST[CMD] = 0b011) is used to lock
critical code segments in the instruction cache. Locked cache blocks are not replaced during misses and
are not affected by invalidate commands. Correct operation of locked instruction cache blocks relies on
software following the procedures described in
Attributes."
To load and lock one or more cache blocks:
1. Read the IC_CST error type bits to clear them.
2. Write the address of the cache block to be locked to the IC_ADR register.
Freescale Semiconductor
22 23
0 = Unlocked
1 = Valid 1 = Locked
Section 7.5.5, "Updating Code and Memory Region Attributes."
Section 7.5.5, "Updating Code and Memory Region
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Table 7-6 provides the format of the IC_DAT
24
LRU code:
1 = way1 is more recent than way0.
0 = way0 is more recent than way1.
Instruction and Data Caches
25-31
Reserved
7-9