Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 113

Instruction
Bus
Embedded
MPC8xx
Processor
Core
Load/Store
Bus
Fast Ethernet
Controller
DMAs
DMAs
FIFOs
10/100
Base-T
Media Access
Control
MIII / RMII
1.2 Embedded MPC8xx Core
The MPC885 family integrates an embedded MPC8xx core with high-performance, low-power
peripherals to extend the Freescale data communications family of embedded processors farther into
high-end communications and networking products.
The core is compliant with the UISA (user instruction set architecture) portion of the PowerPC
architecture. It has an integer unit (IU) and a load/store unit (LSU) that execute all integer and load/store
operations in hardware. The core supports integer operations on a 32-bit internal data path and 32-bit
arithmetic hardware. The core interface to the internal and external buses is 32 bits wide.
Freescale Semiconductor
8-Kbyte
Instruction Cache
Instruction MMU
32-Entry ITLB
8-Kbyte
Data Cache
Data MMU
32-Entry DTLB
Slave / Master IF
4
Parallel I/O
Timers
4 Baud Rate
32-Bit RISC Controller
Generators
Parallel Interface Port
Timers
USB
Figure 1-9. MPC870 Block Diagram
MPC885 PowerQUICC Family Reference Manual, Rev. 2
System Interface Unit (SIU)
Unified
Memory Controller
Bus
Internal
Bus Interface
Unit
System Functions
PCMCIA-ATA Interface
Interrupt 8-Kbyte
Controllers Dual-Port RAM
and Program
ROM
SMC1
Serial Interface Serial Interface
MPC885 Overview
External
Bus Interface
Unit
Virtual IDMA
and
Serial DMAs
2
I C
SPI
1-15