Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 666

Serial Communications Controllers
RCLK
RXD
(Input)
CD
(Input)
NOTES:
1. GSMR_H[CDS] = 0. CDP=0.
2. If CD is negated prior to the last bit of the receive frame, CD lost is signaled in the frame BD.
3. If CDP=1, CD lost cannot occur and CD negation has no effect on reception.
RCLK
RXD
(Input)
CD
(Input)
NOTES:
1. GSMR_H[CDS] = 1. CDP=0.
2. If CD is negated prior to the last bit of the receive frame, CD lost is signaled in the frame BD.
3. If CDP=1, CD lost cannot occur and CD negation has no effect on reception.
Figure 21-12. Using CD to Control Synchronous Protocol Reception
If CD is programmed to envelope the data, it must remain asserted during frame transmission or a CD lost
error occurs. Negation of CD terminates reception. If GSMR_H[CDS] is zero, CD must be sampled by the
SCC before a CD lost error is recognized; otherwise, the negation of CD immediately causes the CD lost
condition.
If GSMR_H[CDS] is set, all CD transitions must occur while the Rx clock is low.
21.4.4.2 Asynchronous Protocols
In asynchronous protocols, RTS is asserted when SCC data is loaded into the Tx FIFO and a falling Tx
clock occurs. CD and CTS can be used to control reception and transmission in the same manner as the
synchronous protocols. The first bit sent in an asynchronous protocol is the start bit of the first character.
In addition, the UART protocol has an option for CTS flow control as described in
UART Mode."
• If CTS is already asserted when RTS is asserted, transmission begins in two additional bit times.
• If CTS is not already asserted when RTS is asserted and GSMR_H[CTSS] = 0, transmission begins
in three additional bit times.
• If CTS is not already asserted when RTS is asserted and GSMR_H[CTSS] = 1, transmission begins
in two additional bit times.
21-20
First Bit of Frame Data
CD Sampled Low Here
First Bit of Frame Data Last Bit of Frame Data
CD Assertion Immediately
Gates Reception
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Last Bit of Frame Data
CD Sampled High Here
CD Negation Immediately
Halts Reception
Chapter 22, "SCC
Freescale Semiconductor