Freescale Semiconductor PowerQUICC MPC885 Reference Manual page 423

Default at Power-On Reset
MODCK[1:2]
MFI[12:15]
00 8
01 15
10 6
11 15
Note: Note: S = 1, MFN = 0, MFD = 1 for all of the reset configurations.
Note: The general system clock[GCLK2] is jdbck divided by 2.
Note: divout1 is jdbck divided by 2.
Under no condition should the voltage on MODCK1 and MODCK2 exceed
the power supply voltage VDDH applied to the part.
At power-on reset, before the PLL achieves lock, no internal or external clocks are generated by the
MPC885, which may cause higher than normal static current during the short period of stabilization.
14.2.4 Crystal Oscillator Support (EXTAL and XTAL)
The MPC885 provides support for crystal oscillator circuits with the oscillator module (OSCM). The
OSCM supports a frequency of 10MHz.
The clock source of OSCM can be provided by a crystal circuit or an external oscillator. If an external
oscillator is used, it should be connected to EXTAL, and XTAL should be left unconnected. If a crystal
circuit is used, it should be connected between EXTAL and XTAL. The crystal circuit is composed of an
on-chip inverting amplifier, an external parallel resonant crystal, two capacitors, and two resistors, as
shown in Figure 14-3. EXTAL is the amplifier input for the crystal circuit; XTAL is the amplifier output.
Example values for the passive components of the crystal circuits are provided in
because this is a sensitive analog circuit, these values cannot be guaranteed. These components may have
to be tuned due to design-specific parasitic capacitance variation due, for example, to layout and board
composition. Careful consideration must be given to component placement and layout, keeping
components as near as possible to the chip and keeping all trace lengths to a minimum. It should be noted
that the sensitivity of crystal circuits to external component values is so great that even probing the circuit
changes its behavior to the point that it may fail to resonate. In practice, experimentation is required to find
an acceptable range of component values, with the final design value being selected in the middle of this
range.
Lastly, it should also be noted that future changes in the device technology (shrinks) may change the
characteristics of the input and output impedance of the on-chip amplifier. Freescale reserves the right to
perform these changes, and designers should be prepared to modify their crystal circuits appropriately
should these changes cause their crystal circuit designs to fail. This risk should be taken into account when
Freescale Semiconductor
Table 14-3. Power-On Reset DPLL Configuration
OSCLK (DPLL and Interface input) General System Frequency (GCLK2)
PDF[27:30]
0000 OSCM Freq
0000 OSCM Freq
0010 EXTCLK Freq
0000 EXTCLK Freq
NOTE
MPC885 PowerQUICC Family Reference Manual, Rev. 2
Clocks and Power Control
40 MHz (for OSCLK freq = 10 MHZ)
75MHz (for OSCLK freq = 10 MHZ)
1:1 Mode (The allowable frequencies on
EXTCLK are 45 MHz to 66 MHz)
75 MHz (for EXTCLK freq = 10 MHZ)
Figure 14-3. However,
14-7